<@U017UPJEGKZ>: Questions are welcome; the SkyWa...
# analog-design
@User: Questions are welcome; the SkyWater pads are not easy to figure out! From what I can see from the layout, the primary ESD diode in the GPIO is not explicitly defined as a device but is implicit in the drains of the output driver N and P devices, coupling to the large areas of N-tap and P-tap that are under the pad and surrounding the output driver FET arrays. The only real (marked) ESD devices are up the top left corner in the cell
. (As a rule, cells with "xres" in the name are found only in the xres I/O cells, and cells with "gpiov2" are found only in the gpiov2 I/O cell.)
I am trying to simulate the entire IO and running into issues with components missing. Should the "sky130_fd_pr__res_generic_po" model be commented out in "sky130_fd_pr__model__r+c.model.spice"? That seems to be the only line in which it is defined.
The IO netlists also seem to include a "sky130_fd_io__condiode" model for which no spice model exists in the PDK
No, the model should not be commented out. This is one of the pull requests that I want to make to the upstream library. I was dealing with the "condiode" model by ignoring it for LVS and including a file with an empty subcircuit into my simulations. I should probably put the empty subcircuit into my custom addition in open_pdks so that the I/O can be simulated.
Ok, I made a dummy file for the diode and the IO seems to simulate. Looking through the netlist I am a bit confused though. From my understanding, any analog input is going to need a second pass ESD structure, but there is no structure present for the pad_a_esd_0 structure
Has implementation of ESD protection changed beyond what I have been reading in textbooks? Or are we expected to provide our own second pass ESD structure