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#analog-design
Title
# analog-design
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Weston Braun

05/08/2021, 5:15 AM
whats the current state of extraction? I just ran the commands that Tim Edwards posted on Apr 21st and looking through the netlist it seems that additional ports were added to my top level netlist and some of the capacitance values are negative. Not sure about the second one being an issue, but the first one is
Copy code
extract all
ext2sim labels on
ext2sim
extresist tolerance 10
extresist
ext2spice lvs
ext2spice cthresh 0.01
ext2spice extresist on
ext2spice
t

Tim Edwards

05/08/2021, 4:24 PM
The problem with negative capacitances is that magic does generate them, as corrections for overlaps between subcells (e.g., subcell A has 1fF, subcell B has 1fF, but they completely overlap, so the actual capacitance is 1fF, not 2fF. Since there is already 1fF in each extracted subcell, the solution is to add -1fF capacitance in the parent cell to compensate). That said, I think magic is doing an incorrect calculation somewhere and it would be helpful to get a minimalist example to debug.