it seems that there is some DRC rule with the overlap of the cap contacts with the other cap layer? So the capacitor layers themselves can overlap, but the vias for the capacitors can not overlap the other capacitor type? So the picture in the PDK info is wrong?

I need to pass some layouts to Calibre to check this. If I read the rules as they are documented, it is not possible to stack the capacitor vias. But I find this very unusual; other processes where I've used stacked MiM caps allowed the vias on top of one another. I drew the diagram based on my experience, and later discovered that when I implemented the rules as specified, I was getting errors, and those errors were consistent with the rules as stated. For the POR circuit, I worked around this by offsetting the capacitors slightly, allowing me to make some use of overlapping, but it's not an ideal layout geometry.

I think the devices from the device generator have a contact over the whole area.

I did a run through Calibre but it is inconclusive because the rule deck that is being run now is the one that was set up for MPW-one, and this particular rule is not in that deck (I think that's SkyWater's mistake). So I'm still not sure, but I am still looking at how the Calibre rule is implemented; I think it may exclude spacing checks for via3 inside the area of cap2m. But I'm not very familiar with Calibre rule syntax, so I need to study the rule deck a bit.