There is a way to do this by writing a custom setup script that first loads a SPICE netlist for the analog block, and then reads the verilog top level module, and assigns them both to the same netlist.
Otherwise, though, I will need to take a look at your example; the fact that the module is behavioral means that netgen is supposed to detect that and automatically treat the module as a black-box. So I'm not sure why that isn't happening.
The purpose of pin matching is that it is otherwise possible (as Weston has noted) to, say, swap plus and minus inputs on an opamp and be none the wiser because the topology is the same. But to compare pins, either (1) the pin names have to be the same in both netlists, or (2) you have to make a very complicated setup file where you tell netgen exactly what pin names are supposed to match each other in both netlists.
I am attaching a variation of your two files (spice and verilog). Your verilog was incorrect to begin with since you declared module "child" but instantiated module "child_v" which does not exist. Mostly I just made sure the module name matches the subcircuit name and the pins all have the same names, and then everything works fine. If you insist on mismatched cell names you can use the "equate classes" command but you should give the canonical form for each class with the circuit included, such as "-circuit1 child" and "-circuit2 child_v". If you insist on having different pin names, it can be handled, but becomes much more complicated in the setup.