I was going to put my whole power stage in a deep nwell for noise isolation. I remember someone talking about extraction for devices in a nwell being partly broken or something. Am I going to be able to produce a LVS clean design after extraction? Is there any precautions I need to take?

Extraction will not work properly for multiple isolated pwell areas inside an nwell. It may or may not be an issue, depending on your layout. In the worst case, if you can prove that it passes LVS without the deep nwell, and you can show that the only LVS error with deep nwell is that supposedly isolated P-regions have been shorted together in the layout netlist, then you're good.

@Tim Edwards I'm working with multiple isolated pwell areas inside an nwell and Magic seems to be ok at it.

* SPICE3 file created from teste.ext - technology: sky130A

.option scale=5000u

X0 D1 G1 S1 B1 sky130_fd_pr__nfet_g5v0d10v5 ad=16000 pd=560 as=16000 ps=560 w=200 l=100
X1 D2 G2 S2 B2 sky130_fd_pr__nfet_g5v0d10v5 ad=16000 pd=560 as=16000 ps=560 w=200 l=100
X2 D3 G3 S3 B3 sky130_fd_pr__nfet_g5v0d10v5 ad=16000 pd=560 as=16000 ps=560 w=200 l=100

Magic extracts the three different bulk terminals. My question is: is it really working alright? Would any design with multiple isolated pwells inside the same deep nwell be fabricated in the next shuttle if it passes Magic DRC?

@Luis Henrique Rodovalho: If everything is drawn in the same cell (i.e., flat) then it should extract correctly. The problems are mostly with having transistors within generated cells or standard cells, and then putting a deep nwell structure underneath that is not in the same cell as the transistors. In that case, the pwell regions are extracted independently of the deep nwell and so get merged together.