Has anyone simulated the extracted netlist from th...
# analog-designw
Weston Braun
06/17/2021, 6:29 PMHas anyone simulated the extracted netlist from the caravan user project wrapper? I am getting weird spice errors despite the fact that it passes lvs
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Tim Edwards
06/17/2021, 6:32 PMYou mean the example project? What sort of errors are you seeing?
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Weston Braun
06/17/2021, 6:35 PMI extracted the netlist (the lvs netlist actually) and and renamed the schematic symbol for the user project wrapper
Weston Braun
06/17/2021, 6:35 PMAnd put that in my testbench and ngspice is giving me really nonsensical errors
Weston Braun
06/17/2021, 6:35 PMI will have to debug tonight more. At work now.
Weston Braun
06/17/2021, 6:36 PMIt thinks wb_clk_I is a module
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Tim Edwards
06/17/2021, 6:41 PMI'll have to refresh my memory on how I ran the simulation for that. I think I just ran a full chip functional simulation with verilog with a behavioral model of the POR circuit to confirm connectivity on the I/O, but all analog simulation was done just on the POR circuit.
Tim Edwards
06/17/2021, 6:43 PMIdeally, it should be possible to run a mixed-mode simulation from the chip top level but I think it will take some work to simulate the I/O without ngspice bogging down. I've simulated a single GPIO pad with ngspice. I'm not sure what happens when you throw an entire padframe at it.
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Weston Braun
06/17/2021, 7:42 PMI am not simulating the entire chip, just the extracted user analog project wrapper.
Weston Braun
06/17/2021, 7:43 PMIt seems like something is getting mangled and there may be a pin order mismatch between the extracted design and the top level schematic symbol or something.
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Tim Edwards
06/17/2021, 8:33 PMThat is quite possible. I may not have simulated in ngspice at the level of the wrapper. I can try to duplicate the issue.
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Weston Braun
06/18/2021, 2:05 AM@Tim Edwards so the first problem is that the pin order does not match between the extracted netlist and xschem
Weston Braun
06/18/2021, 2:06 AMI am a bit confused, I thought that lvs checked both pin order and pin names for matching, does it not?
Weston Braun
06/18/2021, 2:06 AMIs there any easy way to get this to match without breaking the submission process (does the precheck or anything efabless depend on a specific port order?)
Weston Braun
06/18/2021, 2:06 AMalso, even then, I dont really want to rename a million ports
Weston Braun
06/18/2021, 2:27 AMI am getting bizzare errors like "warning, can't find model wb_clk_i"
Weston Braun
06/18/2021, 2:28 AMI wrote a wrapper, so the pin ordering should match