Has anyone simulated the extracted netlist from th...
# analog-design
Has anyone simulated the extracted netlist from the caravan user project wrapper? I am getting weird spice errors despite the fact that it passes lvs
You mean the example project? What sort of errors are you seeing?
I extracted the netlist (the lvs netlist actually) and and renamed the schematic symbol for the user project wrapper
And put that in my testbench and ngspice is giving me really nonsensical errors
I will have to debug tonight more. At work now.
It thinks wb_clk_I is a module
I'll have to refresh my memory on how I ran the simulation for that. I think I just ran a full chip functional simulation with verilog with a behavioral model of the POR circuit to confirm connectivity on the I/O, but all analog simulation was done just on the POR circuit.
Ideally, it should be possible to run a mixed-mode simulation from the chip top level but I think it will take some work to simulate the I/O without ngspice bogging down. I've simulated a single GPIO pad with ngspice. I'm not sure what happens when you throw an entire padframe at it.
I am not simulating the entire chip, just the extracted user analog project wrapper.
It seems like something is getting mangled and there may be a pin order mismatch between the extracted design and the top level schematic symbol or something.
That is quite possible. I may not have simulated in ngspice at the level of the wrapper. I can try to duplicate the issue.
@Tim Edwards so the first problem is that the pin order does not match between the extracted netlist and xschem
I am a bit confused, I thought that lvs checked both pin order and pin names for matching, does it not?
Is there any easy way to get this to match without breaking the submission process (does the precheck or anything efabless depend on a specific port order?)
also, even then, I dont really want to rename a million ports
I am getting bizzare errors like "warning, can't find model wb_clk_i"
I wrote a wrapper, so the pin ordering should match