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#analog-design
Title
# analog-design
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Matthew Guthaus

03/07/2022, 6:07 PM
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Luis Henrique Rodovalho

03/07/2022, 6:45 PM
The minimum diffusion contact width is 420 nm, isn't it? At least, it is for the poly contact.
I don't know why the PDKs allow minimum width transistors smaller than the diffusion contacts... The results are ugly and it wastes area. See those transistors in TSMC 180 nm PDK, for example.
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Matthew Guthaus

03/07/2022, 6:56 PM
Ah, dog bone transistors.
It should still pass DRC though?
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Luis Henrique Rodovalho

03/07/2022, 6:58 PM
I don't think so. Maybe it is a Magic DRC limitation. Maybe it doesn't allow a dog bone transistors. It should pass a commercial tool DRC check.
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Matthew Guthaus

03/07/2022, 7:34 PM
@User I think this is a bug in the DRC deck.
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Tim Edwards

03/07/2022, 7:40 PM
Exactly what are you referring to that you think is a bug in the DRC deck?
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Matthew Guthaus

03/07/2022, 7:40 PM
You cannot draw an NMOS that is 0.36um width which is a valid size.
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Tim Edwards

03/07/2022, 7:44 PM
That's not a bug in the DRC deck. It is an intentional limitation of the parameterized device generator. Strictly speaking, SkyWater states that a MOSFET has a minimum width of 0.42um. That's their DRC rule. Narrower transistors are only allowed in SkyWater-approved standard cell libraries. I have bent the rules a bit by allowing any cell to be given an
<http://areaid.sc|areaid.sc>
layer.
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Matthew Guthaus

03/07/2022, 7:45 PM
Ahhh, I see.
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Tim Edwards

03/07/2022, 7:51 PM
Note that there is a "machine-rule" ("MR") deck made for klayout which matches the SkyWater machine-rule deck for Calibre and specifies all the rules that will cause SkyWater to reject our reticle (or else we have to go through a long process of confirming and waiving each such violation with SkyWater). Ultimately, you can do anything on your chip that does not violate a manufacturing rule, and that includes making transistors down to width of 0.15um. The non-MR rules are basically yield- or performance-related, and so when violating those rules, it's incumbent upon the designer to accept the risk. Ideally, I would at some time like to split the magic DRC deck into MR and non-MR rules, so that you can get a clean result when intentionally violating non-MR rules. As it stands now, only klayout will give you such a result.
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Matthew Guthaus

03/07/2022, 7:52 PM
I see. I have students designing "user rule" memory cells, so this size is important.
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@User How do I add areaid.sc in magic?
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Tim Edwards

03/07/2022, 8:03 PM
I mentioned one way in your cross-post, which is to paint, for example, the
scnmos
device type. That automatically forces the cell to be covered with
<http://areaid.sc|areaid.sc>
.
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Matthew Guthaus

03/07/2022, 8:38 PM
@User I'm not clear how to do that. If I paint scnmos, it doesn't actually change any of the layers and still gives the DRC error...
It still only shoes: Selected mask layers: nmos ( Topmost cell in the window ) ndiff ( Topmost cell in the window ) poly ( Topmost cell in the window )
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Tim Edwards

03/07/2022, 9:02 PM
The device types that are sort of "SkyWater-reserved" are locked to prevent casual use by unwary designers. Use
tech unlock *
, and then you can draw them.
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Matthew Guthaus

03/07/2022, 10:19 PM
@User It looks like 0.36 is wide enough for contacts without the dog bone
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Luis Henrique Rodovalho

03/07/2022, 10:25 PM
@User Then it should be the best width possible considering area for extremely small digital cells. And 0.36/0.15 size is still in the bin.csv file.
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