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#analog-design
Title
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wisla morais
03/20/2022, 2:46 PMHi! I am implementing an analog circuit and I'm have the following errors in the precheck.
Does someone know what this means?
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Arman Avetisyan
03/20/2022, 3:22 PMYou need to have valid netlist in netgen/user_project_analog.spice
It compares them with your GDS
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wisla morais
03/21/2022, 7:14 PMYes. But I'm having problems with extraction. I have a connection on the VSSA1 pin, but in the extraction it shows vccd2.
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Arman Avetisyan
03/22/2022, 5:13 AMis your lvs clean?
I had issue where vss of a lot of components where shorted. This was due to magic/olen pdks version.
This only happened when the cells where located on dnwell. I flattened the design and it fixed the issue
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wisla morais
03/22/2022, 2:51 PMI was implementing two blocks and connected them as cells in the user_analog_project_wrapper_empty. The lvs is clean when I run each block separately. But when I insert the blocks to the top, the VSSA1 pin is extracted as VCCD2 and fails the pre-check. I'm using magic layout.
I received the following message in the precheck: " PORTS CHECK FAILED: user_analog_project_wrapper ports do not match the golden wrapper ports. Mismatching ports are : ['vssa1']".
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Tim Edwards
03/22/2022, 3:29 PMCan you post a link to your layout?
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wisla morais
03/22/2022, 6:57 PMThis is the repository with the envelope detector and OTA blocks: https://github.com/wislamilena/receiver.git
I made the submission yesterday just the envelope detector ( this is the repository: https://github.com/wislamilena/my-chip.git). The top with just that block passed the precheck. When I put the other block (OTA), the problems appeared and I couldn't solve them before the submission deadline.
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Tim Edwards
03/22/2022, 7:19 PMIn your
otaV5VpVnvccd2Vnvccd2vssa1w
wisla morais
03/23/2022, 12:13 PMAh, I understand! Thank you. Will there be a deadline to update the repository for tapeout?
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