I'm trying to simulate a simple R2R DAC using the sky130_fd_pr__res_high_po_1p41 modules and I keep running into convergence failures in ng-spice after the initial operating point has been found and the transient simulation has started.
In the attached netlist, if you comment out the res_high_po_1p41 models and un-comment the ideal resistors, everything works fine.
With the res_high_po_1p41, increasing the risefall time of the vpulses to, say, 0.5ns will allow ng-spice to finish the simulation.
This DAC was taken from a sar adc, where the clock rise/fall time is 1ns (which I think is a realistic number), so the rise/fall of the pulses going into the DAC is whatever a sky130_fd_sc_hvl__dfxtp_1 naturally produces at the Q port, and the convergence failure was happening there. I made this simpler testcase to isolate the problem.
So my question is, before I start trying other simulations, is there any option I can set, or anything else I could do, that would allow the transient simulation to finish without convergence errors?