I'm trying to simulate a simple R2R DAC using the ...
# analog-design
I'm trying to simulate a simple R2R DAC using the sky130_fd_pr__res_high_po_1p41 modules and I keep running into convergence failures in ng-spice after the initial operating point has been found and the transient simulation has started. In the attached netlist, if you comment out the res_high_po_1p41 models and un-comment the ideal resistors, everything works fine. With the res_high_po_1p41, increasing the risefall time of the vpulses to, say, 0.5ns will allow ng-spice to finish the simulation. This DAC was taken from a sar adc, where the clock rise/fall time is 1ns (which I think is a realistic number), so the rise/fall of the pulses going into the DAC is whatever a sky130_fd_sc_hvl__dfxtp_1 naturally produces at the Q port, and the convergence failure was happening there. I made this simpler testcase to isolate the problem. So my question is, before I start trying other simulations, is there any option I can set, or anything else I could do, that would allow the transient simulation to finish without convergence errors?
Are you using ngspice with the set ngbehavior=hsa option?
set ngbehavior=hsa set ng_nomodcheck
The sky130_fd_pr__res_high_po_1p41 resistors do simulate fine under most conditions. I've also used mosfets and bjts without issue
The was a yes to "Are you using ngspice with the set ngbehavior=hsa option?" by the way. I just pasted my .spiceinit
I just tried to run your example and i confirm that i get the same issue with my setup. 1ns finishes fine 0.1ns aborts during simulation.
worked for me on this smaller testcase, but I still have convergence failures on larger testcases. Xyce is able to simulate these without problems, after translating the netlists, and in a fraction of the time.
I was facing this problem too I tried to a lot of things to fix it but didn't work I'll xyce and confirm on this