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#analog-design
Title
# analog-design
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Leonardo Gomes

04/28/2022, 2:20 AM
60 GHz VCO, still ongoing 🙂 • Done (more or less): ◦ CCP ◦ Varactor banks ◦ Inductor plus guard ring ◦ Buffer fet connections • To do: ◦ Buffer loads (microstrips) ◦ CCP current mirror ◦ RF pads ◦ Biasing, biasing everywhere! ◦ Figure out about the placement of density tiling inside the top cell (HALP!) Simulations tells me that it oscillates at around 60GHz with a FTR of 4.5% (taking into account most of the parasitic loading sans inductances)
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Alexander Sheldon

04/28/2022, 4:15 AM
Are your files hosted on github? what kind of noise performance are you getting? I would be interested in to see how well this agrees in measurements when it gets fabricated
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Ryan Wans

04/28/2022, 9:07 AM
To remove density filling in certain areas, make sure you display unused layers in Klayout and use the metal blockage layers, metal1 block is 68/10 for example, to prevent filling in that area
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Then just do that for each metal layer in the cell.
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yrrapt

04/28/2022, 9:56 AM
Looking nice, how much current do you bias this with?
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Leonardo Gomes

04/28/2022, 2:52 PM
Lots of questions, I'll answer then in order :) @User No, not yet on GitHub. I have to learn how to use it. (Yes, I am that kind of noob). And, no, no phase noise results. I'm doing it in S-parameters, since I still don't know how to add an equivalent circuit for the microstrips (aside from a very long RLGC circuit, that is) @User I designed nominal the biasing of the CCP to be at 10mA (0.15mA/um for each half of the CCP). I had to overdesign it since there's a lot of uncertainties :)
The Qfactor of the varactors will more or less dominate the Q of the tank, and it drops do 2 at maximum capacitance, so that's that... I'm expecting pretty poor noise performance, but hey, that's only a demonstrator. If it works well I have bigger plans for a next iteration 3:)
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Tim Edwards

04/28/2022, 3:15 PM
@User: Try to avoid blocking too much fill, or you will end up violating the overall chip fill density requirement. So keep the fill blockage to a minimum. What some designers do in this case is to pre-fill the area around the inductor, and then run a field equation solver to get the inductor parameters including the fill. That way you get to control the impact that the fill has on the circuit. But I don't think that this inductor is large enough to be an issue with overall fill density, especially if you don't have inductors all over your project area. Also, since the density is calculated for the whole chip, you can offset the lack of density around the inductor by putting large plates of metal elsewhere in the design.
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Leonardo Gomes

04/28/2022, 3:21 PM
That's interesting to know. I was afraid of maximum/minimum local density rules. Since it's only full chip, some solid squares of metal will be placed at dead corners 3:)
Also, how do I run antenna DRC and the density check?
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Tim Edwards

04/28/2022, 3:25 PM
There are scripts for antenna and fill generation and density checks that are included with the open_pdks installation of sky130; you'll find them under `libs.tech/magic`:
check_antenna.py
,
generate_fill.py
, and
check_density.py
. It is the same fill generation script that we use for tapeout, so if you run that followed by a density check, it should give the same result as you will get back from tapeout checks.
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Rob Taylor

05/04/2022, 9:18 AM
What are you using for simuation?
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