Hail Hydra The basic VCO floorplan is quite done,...
# analog-design
Hail Hydra The basic VCO floorplan is quite done, me thinks. For now I have about 430 um x 340 um of surface. I have completed the layout of all the major blocks of the circuit, which are:
Biasing current mirror
Buffer mosfets, load and impedance-matching
Differential varactor banks
Inductor plus guard ring
Now I have to re-extract parasitics on the top cell connections (plus parasitics on the current mirror, which haven't been extracted yet ^^' ) and start worrying about the chipathon project submission - and to upload it to github 🙂 PS: the RF pad is merely a placeholder. I feel like it deserves a bit more care - the parasitics are too large, I'm afraid.
I don't think you can output a 60 GHz signal out of those pads, but you can try. Maybe you could make a frequency divider using CML logic and output it. If it can work with 60 GHz, I don't know
The problem is the shunt capacitance between M5 and ground. I'll try to minimize it somehow, but maybe the back-end won't let me :/
I don't know what is that M5 you're talking about. By the way, what is your goal with this VCO?
The topmost metal in the back-end of sky130 is M5. My goal is to design a proof of concept, that a low-cost technology and open-source design tools can lead to a functional mm-wave design
I'm sure this project is a good candidate for chipathon. They have a goal to integrate many projects into one, so it also could be used with other projects that lacks high speed oscillators. RF design is really unexplored here. Good luck!
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