@User How did you deal with that ?

didn’t notice, can you refer to script and line number?

I'm looking at https://github.com/efabless/openlane/tree/master/docker_build/docker and there are

yosys

and

antmicro_yosys

.

I see, in my case I was just using may previously installed version

So what tools did you / didn't you install ? You just tried running the flow and then fix when you got to an error ?

ok, its a bit tricky because I didn’t start clean, I did magice, yosys, qflow, opensta, openroad, openlane, I’m thinking you may be ok just building openroad and adding yosys, vlog2Verilog. Then you still need to change the tcl files so it will use the *_or procs

@tnt: The antmicro version is not currently used but is available as an option. The difference is that the antmicro one has much better SystemVerilog support, and if it performs equally well on pure verilog designs, then we can make it the default.

If it has better SV support, why is that not pushed upstream instead ?

I believe that there are some optimizations specific for Ibex (see https://github.com/antmicro/ibex-yosys-build/), which is the main focus of that build as far as I understand. Perhaps @mkk can elaborate on this.