Ahmed Ghazy
07/27/2020, 2:08 PMThis is a known issue. . . It has found symmetries and is trying to resolve them with some very badly written method. For all practical purposes, it is done, and the circuit is LVS clean.
20Mhz
07/27/2020, 2:09 PMAhmed Ghazy
07/27/2020, 3:59 PM20Mhz
07/27/2020, 4:14 PMLVS Done.
LVS reports:
net count difference = 0
device count difference = 0
unmatched nets = 0
unmatched devices = 0
unmatched pins = 2
property failures = 0
Total errors = 2
(no matching pin) |VPWR
(no matching pin) |VGND
Ahmed Ghazy
07/27/2020, 6:28 PM20Mhz
07/27/2020, 6:32 PMTim Edwards
07/27/2020, 6:43 PM20Mhz
07/27/2020, 6:53 PMTim Edwards
07/27/2020, 7:34 PMtnt
07/27/2020, 8:00 PMAhmed Ghazy
07/27/2020, 9:39 PMvlog2Verilog
to skip the module ports in order to evade having a duplicate of the power ports?