https://open-source-silicon.dev logo
#openlane
Title
# openlane
m

mshalan

08/03/2020, 6:12 PM
@User Why not harden them as one macro (no hierarchy)? Just flatten your SoC core as long as it is digital. Probably you will end up with 20-30k cells (unless you have an accelerator or a similar complex block on the bus). We tried out this approach with designs up to 300K logic cells.
m

Matt Venn

08/03/2020, 6:27 PM
Because I want to incorporate other people's small designs in one aggregated IC.
m

mshalan

08/03/2020, 6:28 PM
I see. The support will be released soon.
This is what I'm working toward
So I want to use my first application to test the 'multi design harness'
m

mshalan

08/03/2020, 6:33 PM
Sounds interesting
it intersects with some ongoing unannounced efforts