@User Why not harden them as one macro (no hierarchy)? Just flatten your SoC core as long as it is digital. Probably you will end up with 20-30k cells (unless you have an accelerator or a similar complex block on the bus). We tried out this approach with designs up to 300K logic cells.

Because I want to incorporate other people's small designs in one aggregated IC.

I see. The support will be released soon.

Sounds interesting