lets see if this does the trick

LevFanin = Abc_ObjReverseLevel( pFanin );
                if ( LevFanin >= Lev ) {
									printf("Network %s\n", pFanin->pNtk->pName);
								}
                assert( LevFanin >= Lev );

missed.

ABC: + mfs
ABC: Assertion failed: (LevFanin >= Lev), function Abc_NtkUpdateReverseLevel, file src/base/abci/abcTiming.c, line 1362.

mmm…

Network: 110
Abc_NtkFastExtract: Nodes have duplicated fanins. FX is not performed.
+ mfs
Network netlist

I wonder if it means this thing

.names ys__n110 ys__n86 ys__n112 ys__n113
1-0 1
-11 1

maybe this one

printf("Network %s \n",  Abc_ObjName(pFanin));

Abc_NtkFastExtract: Nodes have duplicated fanins. FX is not performed.
+ mfs
Network n526734

Just changed synthesis strategy to script #3 and now it produced a netlist

Area for cell type \rstgen is unknown!
   Area for cell type \ahbuart is unknown!
   Area for cell type \ahbjtag is unknown!
   Area for cell type \mctrl is unknown!
   Area for cell type \apbuart is unknown!
   Area for cell type \irqmp is unknown!
   Area for cell type \gptimer is unknown!
   Area for cell type \apbps2 is unknown!
   Area for cell type \grgpio is unknown!
   Area for cell type \grethm is unknown!
   Area for cell type \saed32_inpad is unknown!
   Area for cell type \clkgen_saed32 is unknown!
   Area for cell type \saed32_outpad is unknown!
   Area for cell type \apbctrlx is unknown!
   Area for cell type \saed32_iopad is unknown!
   Area for cell type \syncrambw is unknown!
   Area for cell type \saed32_syncram is unknown!
   Area for cell type \memrwcol is unknown!
   Area for cell type \sky130_fd_sc_hd__buf_2 is unknown!

   Chip area for module '\leon3mp': 7875315.552055


yosys> write_verilog -noattr -noexpr -nohex -nodec /Users/ronaldv/Projects/repositories/openlane/designs/leon3mp/runs/07-08_20-48//results/synthesis/leon3mp.synthesis.v

18. Executing Verilog backend.
Dumping module `\leon3mp'.

Warnings: 6201 unique messages, 6201 total
End of script. Logfile hash: 2d2426fdd9, CPU: user 399.79s system 11.23s
Yosys 0.9+2406 (git sha1 000fd081, clang 11.0.3 -fPIC -Os)
Time spent: 87% 2x abc (2605 sec), 3% 33x opt_clean (97 sec), ...

Able to run placement and cts now, however I need to resolve the black boxes before being able to route, this mean we need RAM, PLL and IOs. Core seems to be about 5mm per side. 1M components

no point on cloning yet, i still have a lot of missing reference, will take a look to simulations now…

sim working now

[Sat Aug 08 13:23:45 ronaldv@Ronalds-MBP16:~/Projects/repositories/leon3mp_yosys ] $ make run_sim
cd sim && ../VHDL/testbench
../../src/ieee/v93/numeric_std-body.vhdl:2151:7:@0ms:(assertion warning): NUMERIC_STD.TO_UNSIGNED: vector truncated
LEON3 MP Demonstration design
GRLIB Version 2020.2.0, build 4254
Target technology: inferred  , memory library: inferred
ahbctrl: AHB arbiter/multiplexer rev 1
ahbctrl: Common I/O area disabled
ahbctrl: AHB masters: 3, AHB slaves: 8
ahbctrl: Configuration area at 0xfffff000, 4 kbyte
ahbctrl: mst0: Cobham Gaisler          LEON3 SPARC V8 Processor
ahbctrl: mst1: Cobham Gaisler          AHB Debug UART
ahbctrl: mst2: Cobham Gaisler          JTAG Debug Link
ahbctrl: slv0: Cobham Gaisler          Simple SRAM Controller
ahbctrl:       memory at 0x00000000, size 16 Mbyte, cacheable, prefetch
ahbctrl:       memory at 0x40000000, size 16 Mbyte, cacheable, prefetch
ahbctrl:       memory at 0x20000000, size 16 Mbyte
ahbctrl: slv1: Cobham Gaisler          AHB/APB Bridge
ahbctrl:       memory at 0x80000000, size 1 Mbyte
apbctrl: APB Bridge at 0x80000000 rev 1
apbctrl: slv1: Cobham Gaisler          Generic UART
apbctrl:       I/O ports at 0x80000100, size 256 byte
apbctrl: slv2: Cobham Gaisler          Multi-processor Interrupt Ctrl.
apbctrl:       I/O ports at 0x80000200, size 256 byte
apbctrl: slv3: Cobham Gaisler          Modular Timer Unit
apbctrl:       I/O ports at 0x80000300, size 256 byte
apbctrl: slv7: Cobham Gaisler          AHB Debug UART
apbctrl:       I/O ports at 0x80000700, size 256 byte
apbctrl: slv11: Cobham Gaisler          General Purpose I/O port
apbctrl:       I/O ports at 0x80000b00, size 256 byte
grgpio11: 8-bit GPIO Unit rev 3
gptimer3: Timer Unit rev 1, 8-bit scaler, 2 32-bit timers, irq 8
irqmp: Multi-processor Interrupt Controller rev 4, #cpu 1, eirq 0
apbuart1: Generic UART rev 1, fifo 4, irq 2, scaler bits 12
srctrl0: 32-bit PROM/SRAM controller rev 0
ahbjtag AHB Debug JTAG rev 2
ahbuart7: AHB Debug UART rev 0
leon3_0: LEON3 SPARC V8 processor rev 3: iuft: 0, fpft: 0, cacheft: 0
leon3_0: icache 1*4 kbyte, dcache 1*4 kbyte

**** GRLIB system test starting ****
Basic memory test
subtest 1
subtest 2
subtest 3
subtest 4
LEON3 SPARC V8 Processor
  CPU#0 register file
  CPU#0 multiplier
  CPU#0 cache system
  CPU#0 memory management unit
Multi-processor Interrupt Ctrl.
Modular Timer Unit
  timer 1
  timer 2
  chain mode
Generic UART
Test passed, halting with IU error mode