is there a reason why all those cells are on that list ? (I know one previous reason mentioned was to keep runtime decent because of there being so many cells)

Actually running time is not one of the reasons. First, there are some cell types that you don't want to use in synthesis like, for example, delay cells and clock buffers (since CTS is a separate step that would insert the clock buffers). Second, some of the cells, back when this list was created, had hard-to-access pin shapes, so the detailed router didn't manage to do routing cleanly. However, this list is likely over-constraining, and if you have done experiments allowing smaller sizes incrementally and still got clean routed layouts, please let us know your findings, or better yet, submit a pull request at open_pdks with a suggested no_synth list. The above should and will be documented under https://github.com/efabless/openlane/blob/master/doc/PDK_STRUCTURE.md soon.

@Ahmed Ghazy ok thank you for that, along the line of what I was expecting

@AndrewSftD refer to this and that since you're running experiments. They should be a great help. Also the version of this on the develop branch is more powerful.

yeah, the wiki is what i was refering to above. second sugestion makes a lot of sense and does look like it will help, i will give a try later and i will pull dev as well

@AndrewSftD: There's another release by Mohamed Kassem's dial-up talk; there are always going to be issues that we discover and fix or report in one of the tools, but we hope by then that things will be stable enough for the shuttle.