Actually running time is not one of the reasons. First, there are some cell types that you don't want to use in synthesis like, for example, delay cells and clock buffers (since CTS is a separate step that would insert the clock buffers). Second, some of the cells, back when this list was created, had hard-to-access pin shapes, so the detailed router didn't manage to do routing cleanly. However, this list is likely over-constraining, and if you have done experiments allowing smaller sizes incrementally and still got clean routed layouts, please let us know your findings, or better yet, submit a pull request at open_pdks with a suggested no_synth list.
The above should and will be documented under
https://github.com/efabless/openlane/blob/master/doc/PDK_STRUCTURE.md soon.