I am encountering a mismatch of nets during the LVS check. The no. of device instances match. When I checked the LVS report, the missing nets in the schematic are those involving VGND and VPWR. Any idea what could be causing this error? Circuit 1 contains 716828 devices, Circuit 2 contains 716828 devices. Circuit 1 contains 184338 nets, Circuit 2 contains 183262 nets. * MISMATCH **

Could you share the verilog netlist?

@Ahmed Ghazy Do you mean the <design>.synthesis_preroute.v file in the path runs/<tag>/results/synthesis or the netlist file (<design>.lvs.v) in the path runs/<tag>/results/lvs?

The

lvs.v

one; it looks like it somehow doesn't have the power connections.

@Ahmed Ghazy Here's the file

@Harikumar S: the verilog netlist looks fine. Could you share the spice netlist as well?

@Ahmed Ghazy I have an issue with accessing my remote system in the lab. So, I will share the spice netlist as soon as the situation is resolved.

I had a look, and there are clear breaks in the power connections, suggesting that something went wrong with PDN generation. Is there anything suspicious in the PDN logs?

Sure, I'll have a look for discrepancies in the PDN logs.