does openlane support VHDL?

I think yosys, the synth, only supports verilog but it seems some people are working on vhdl, for example you could look at this project: https://github.com/ghdl/ghdl-yosys-plugin

Not currently, but we've been planning to try the above plugin for a while.

I hacked it to place leon3mp design, it’s usable