Hello Guys, so I added my own design (a single bit comparator) but it only contains config.tcl and not skywater_...._.config.tcl file. How can I generate one for my design since the specifications seem to be different for every design. also when i try to run it using flow.tcl it gives an error [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. 1. Executing Verilog-2005 frontend: /openLANE_flow/designs/comp/src/one_bit_equal_comp.v Parsing Verilog input from `/openLANE_flow/designs/comp/src/one_bit_equal_comp.v' to AST representation. Generating RTLIL representation for module `\one_bit_equal_comp'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). ERROR: Module `comp' not found! [ERROR]: during executing: "yosys -c /openLANE_flow/scripts//synth.tcl -l /openLANE_flow/designs/comp/runs/24-09_09-30//logs/synthesis/yosys.log |& tee >&@stdout" [ERROR]: Last 10 lines: child process exited abnormally [ERROR]: Please check yosys log file [ERROR]: Dumping to /openLANE_flow/designs/comp/runs/24-09_09-30//error.log while executing "try_catch [get_yosys_bin] -c $::env(SYNTH_SCRIPT) -l $::env(yosys_log_file_tag).log |& tee $::env(TERMINAL_OUTPUT)" (procedure "run_yosys" line 5) invoked from within "run_yosys" (procedure "run_synthesis" line 4) invoked from within "run_synthesis" (procedure "run_non_interactive_mode" line 9) invoked from within "run_non_interactive_mode {*}$argv_copy" invoked from within "if { [info exists flags_map(-interactive)] ||\ [info exists flags_map(-it)] } { if { [info exists arg_values(-file)] } { run_file [file normali..." (file "./flow.tcl" line 149)

@ibad1112 Here, it says that that you are using a module

comp

that doesn't exist in the list of verilog files that you passed to Yosys. So that's the issue. Check ::env(VERILOG_FILES) and the includes inside your source code