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I'm trying to make Openlane flow work with the OSU 45nm PDK. Based on my experience, the common_pdn.tcl file seems to be playing a very important role in the DRC errors encountered, especially the rails part of the pdngen::specify_grid stdcell block. Can I have some guidance on assigning the metal width, spacing and offset values of this part of the code?

Initially I went with the following piece of code:   metal1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0} ; But this gave rise to a lot of overlap errors during the SPICE extraction.

Then I changed it to : metal1 {width 0.17 pitch 2.4 offset 0} The overlap errors are resolved now but this in turn gave rise to a lot of routing violations in spite of using TR14.

<@U016HSALFAN> is there any specific methodology to assign these values?

<@U018K9ZBU9J> Ideally, you want the width to cover the power pins so it should be wide enough to do so. Then you'd use the pitch and the offset to make sure that all power and ground pins are covered which is basically the SITE HEIGHT. That's for the rails. As for the straps, you need to make sure that at least 2 stripes cross the design.

<@U01634FSETZ> I figured that the width of the rail is causing the issue. I fixed the pitch to equal the SITE HEIGHT and set the offset to 0. When the width is 0.48, there are no routing violations but there are a lot of overlap errors. When the width is set to 0.17, there are no overlap errors during SPICE export but there are routing violations. Does that mean I have to use a trial and error strategy to find the optimum width of the rail? Correct me if I'm wrong.