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<@U016HSALFAN> remember we were talking about addi...
# openlane
m
@User remember we were talking about adding that tiny inverter design to the examples?
I've recently re-installed the whole flow and got the inverter to work
but I really want to do it without a clock
you said I could do this with set ::env(CLOCK_TREE_SYNTH) 0
but with that set, and the register removed from the inverter
I get this error:
image.png
I've tried fiddling about with the density, utilisation and pdn options but always get this same error
do you know any working examples that don't have a clock?
a
https://github.com/efabless/openlane/tree/develop/designs/digital_pll_sky130_fd_sc_hd However, unlike the digital_pll the issue here is that the design is too small. So maybe try using an absolute FP_sizing and skipping initial placement but this feature is not yet in master. An example configuration of a tiny design that doesn't have a clock looks like this:
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set ::env(RUN_SIMPLE_CTS) 0
set ::env(CLOCK_TREE_SYNTH) 0
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 160 160"
set ::env(PL_TARGET_DENSITY) 0.20
set ::env(SYNTH_MAX_FANOUT) 6
set ::env(PL_SKIP_INITIAL_PLACEMENT) 1

set ::env(FP_PDN_VOFFSET) 4
set ::env(FP_PDN_VPITCH) 6
set ::env(FP_PDN_HOFFSET) 0
set ::env(FP_PDN_HPITCH) 9
We're conducting some final tests and rc3 will be coming over the weekend. So, then you'll be able to use 
PL_SKIP_INITIAL_PLACEMENT
m
great
thanks!
btw what branch should I be making pull requests to for adding example designs?
a
develop
m
ok!
Hi @Amr Gouhar and @Ahmed Ghazy
I have updated to rc3
to play with this and with the SoC features
here's the src and config
and the failiure I'm getting:
Screenshot from 2020-10-12 17-14-22.png
any clues appreciated!
a
Hi @Matt Venn, try adding the following lines in your config:
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set ::env(CLOCK_PERIOD) 0
set ::env(CLOCK_TREE_SYNTH) 0
m
ok that's moved me on a bit
now I get failure in global placement
floorplan has worked though
Screenshot from 2020-10-12 17-24-04.png
removing set ::env(PL_SKIP_INITIAL_PLACEMENT) 1
has got me a bit further
Screenshot from 2020-10-12 17-28-16.png
looks like PDN is failing now
Screenshot from 2020-10-12 17-29-08.png
probably design is smaller now so the settings that worked previously for clocked inverter are now failing
a
try out absolute sizing, it wouldn't make a difference for the floorplanner but it does for the global placer. example:
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set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 160 160"
set ::env(PL_TARGET_DENSITY) 0.20
set ::env(PL_SKIP_INITIAL_PLACEMENT) 1
Also, try removing:
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set ::env(FP_PDN_VOFFSET) 15
set ::env(FP_PDN_VPITCH) 5
set ::env(FP_PDN_HOFFSET) 15 
set ::env(FP_PDN_HPITCH) 5
The configurations should self adjust for the pdn in rc3 (hopefully to the correct values)
if it didn't then maybe an exploration on a large range of values for pdn would help. Check this for more.
m
that brings the failure back to the replace
a
small designs can be tricky to configure, but running an exploration should speed up the process
m
ok,
any opinion on exploring density with absolute sizing or pdn settings with non-absolute?
or is there any other setting worth exploring with absolute
a
So far, fixing an absolute size with low density and manipulating pdn configurations seemed to work for me pretty well. But, I've never tried a design composed of one standard cell. Still, it would be a good starting point.
m
ok, I'll give it a go thanks
a
@Matt Venn: I can't help but wonder why you're trying to harden a design with only one cell?:)
m
because I think it will be useful to help complete beginners how this stuff works
even a clocked inverter when hardened contains a lot of 'unexpected' stuff
so I want to have a series: inverter -> clocked inverter -> counter -> 7 segment led driver
if I show the 7 segement counter as the first example it's going to be hard for people to see how the hdl actually gets mapped to silicon
a
Got it; useful for educational reasons for sure 👍
What Amr recommends above should work; definitely try removing the PDN configs you have as it should self-adjust. Also, an alternative to absolute sizing is to try extremely low core utilizations (1% or maybe even less?).
m
OK I'm a bit confused
remove PDN configs, but then what parameter should I iterate over?
a
I would try increasingly lower and lower core utilizations and placement densities.
I have a meeting in 5 mins, but I can try hardening it myself afterwards if it didn't work for you.
m
ok that would be great
couple of quick questions about run_designs
its not clear to me what I have to provide in the configuration file --regression
anything I want? and the rest are taken from the normal config.tcl?
Screenshot from 2020-10-12 18-00-21.png
a
this is one example of a configuration file. The generated configurations are actually appended to the config.tcl (for each run).
and you can change/iterate over any configuration you want
m
the docs say "all possible combinations of the passed regression file"
but it's unclear to me what the above file would do
there doesn't seem to be a 'combination' to me
like how would I configure it to explore core utililisation?
a
maybe try writing a config file: densUtil.config
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FP_CORE_UTIL=(25 50 60)
PL_TARGET_DENSITY=(0.5 0.6)
and run
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python3 run_designs.py -d spm -t testExploration -th 6 -r densUtil.config
pointing to the densUtil.config This should clear up what the script does, you'll find a couple of configuration files generated under spm and 6 runs will be started.
m
thanks. So the stuff in brackets are the combinations to check
a
Yes
m
ok yes thanks now I get it
a
can you change that to a PR to develop?
m
done
a
Thanks!
m
anyway to find out how the combinations went? It looks like there is some tool that tries to run after but it seems very broken
I just search the config_regression_[0123456] directories to see how far they each got?
a
after their completion you'll find a summary generated under the regression_results folder. Check this.
m
thanks
ok sweet I am running a lot of combinations on 20 threads
all failed 😞
FP_CORE_UTIL=(1 25 50 60 90) PL_TARGET_DENSITY=(0.01 0.1 0.4 0.8)\
that was what I tried
a
@Matt Venn: I would try
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FP_CORE_UTIL=(0.1 0.5 1 2 3 4 5)
as well.
m
ok thanks
btw I have added this to my repo: https://github.com/mattvenn/clockless-inverter
so you can see the config too
also all failed with your suggestion @Ahmed Ghazy
I'm also unable to get a clocked inverter routed
so maybe something has happened in rc3 that makes it harder to harden small designs.
I did try to push https://github.com/mattvenn/openlane/blob/master/designs/inverter/config.tcl to the design library, but probably didn't make it to develop
would be good to get a small design as part of the regression tests
that config.tcl linked above does make it quite a way, but fails on triton - it apparently can't find a clock net
anyway, I have to head off now
a
@Matt Venn: I'll try out your design as soon as I can (probably early tomorrow). Thank you very much for bringing this up! and definitely once we find the proper configurations, it would be a huge help to PR this to develop.
m
Thanks! Very happy to contribute when I can.
I also have a clocked branch in that repo
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