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Mitch Bailey

10/19/2020, 9:33 AM
I noticed that the test design picorv32a has buffers with no input. Is this known and intentional? Hi-Z input to inverters is generally not a good thing. Here's a sample from the powered verilog used for LVS. designs/picorv32a/runs/*/results/lvs/picorv32a.lvs.powered.v
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sky130_fd_sc_hd__buf_2 _31169_ (
  .A(mem_la_wdata[7]),
  .VGND(VGND),
  .VPWR(VPWR),
  .X(pcpi_rs2[7])
 );
 sky130_fd_sc_hd__buf_2 _31170_ (
  .VGND(VGND),
  .VPWR(VPWR),
  .X(trace_data[0])
 );34
 sky130_fd_sc_hd__buf_2 _31171_ (
  .VGND(VGND),
  .VPWR(VPWR),
  .X(trace_data[1])
 );
31169 is as expected - input 'A' has a net assigned. However, 31170, 31171, and 34 other instances are missing connections to the buffer input 'A'. This appears to lead to a floating input in the final layout.
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Ahmed Ghazy

10/19/2020, 2:23 PM
@Mitch Bailey: That's a good catch. In the RTL source, you can find:
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if (!ENABLE_TRACE)
			trace_data <= 'bx;
Since the parameter ENABLE_TRACE is set to 0, those ports are expected to be floating. However, we were already forcing such undefined signals to be tied down to 0, but this was being done incorrectly after HI LO constant mapping. This has now been fixed in https://github.com/efabless/openlane/commit/0882565dd09d513c1965aa92ffdf21d8373f6c7d; thanks for noting this!
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Mitch Bailey

10/20/2020, 12:25 AM
@Ahmed Ghazy Glad to be of help. The open source system CVC that I developed and plan to present at WOSET 2020 is designed to catch errors like this that can easily slip through other verification flows.