open-source-silicon.dev

<@U016Y9FMA2Y> post a link to your design

`module brqrv_core (`
  `16     parameter bit                 PMPEnable        = 1'b0,`
  `17     parameter int unsigned        PMPGranularity   = 0,`
  `18     parameter int unsigned        PMPNumRegions    = 4,`
  `19     parameter int unsigned        MHPMCounterNum   = 0,`
  `20     parameter int unsigned        MHPMCounterWidth = 40,`
  `21     parameter bit                 RV32E            = 1'b0,`
  `22     parameter brqrv_pkg::rv32m_e   RV32M            = brqrv_pkg::RV32MFast,`
  `23     parameter brqrv_pkg::rv32b_e   RV32B            = brqrv_pkg::RV32BNone,`
  `24     parameter brqrv_pkg::regfile_e RegFile          = brqrv_pkg::RegFileFF,`
  `25     parameter bit                 BranchTargetALU  = 1'b0,`
  `26     parameter bit                 WritebackStage   = 1'b0,`
  `27     parameter bit                 ICache           = 1'b0,`
  `28     parameter bit                 ICacheECC        = 1'b0,`
  `29     parameter bit                 BranchPredictor  = 1'b0,`
  `30     parameter bit                 DbgTriggerEn     = 1'b0,`
  `31     parameter bit                 SecureIbex       = 1'b0,`
  `32     parameter int unsigned        DmHaltAddr       = 32'h1A110800,`
  `33     parameter int unsigned        DmExceptionAddr  = 32'h1A110808`
  `34 )` 
This is complete, do you see why it is giving  this error.`/openLANE_flow/designs/brqrv_core/src/brqrv_core.sv:16: ERROR: syntax error, unexpected TOK_PARAMETER`

Don't you need #() for parameters? Also, the open source version yosys doesn't support system verilog, so I don't think your brqrv_pkg:: lines are going to work

yeah i think you need

```module brqrv_core #(
  parameter ...
)(
  input wire ...
);```


see these examples <https://www.chipverify.com/verilog/verilog-parameters>

It was originally like that. <@U01837QU37V>
`module brqrv_core #(`
  `parameter ...`
`)(`
  `input wire ...`
`);`
 I missed it while posting it here. In short this does not work

<@U0172QZ342D> Then that means I wont be able to run it and its not the syntax that is the problem rather YOSYS itself?

I think the problem is that `int`, `bit` are systemverilog types and therefore yosys won't suppor them either

i've never used SV but that's is what <https://en.wikipedia.org/wiki/SystemVerilog|wikipedia says>

otherwise yosys has no problem with parameterised modules in regular verilog

Yes I agree. You need to get it to work with open source version of yosys. Which means not systemverilog