i still haven t managed to successfully place a macro and ro

Question

i still haven t managed to successfully place a macro and route around it i have played with all manner of sizings `FP CORE UTIL` `PL TARGET DENSITY` making sure to keep the die area larger than the placed macros either `replace` fails because `decrease init density penalty` or I get to the end of the flow and the antenna placement fails I have to run <https github com growly openlane blob develop designs 250 tile tcl|the custom script suggested> to make any progress interestingly even without manually placing the macro i can get to the end of the flow and run into the same antenna failures in `or diodes tcl`

aryap · Answer

i can t see what is materially different about the caravel `mgmt core config tcl` to suggest doing it that way

Amr Gouhar · Answer

< aryap> As far as I know antenna insertion amp checking doesn t work on the top level by top level I mean a design where only macros exist no std cells so you ll have to skip these steps don t include them in your interactive script for now < Ahmed Ghazy> correct me if I m wrong

Ahmed Ghazy · Answer

< aryap> < Amr Gouhar> Antenna insertion works but checking needs antenna information the LEFs

Ahmed Ghazy · Answer

< aryap> There is an example on develop now at That has 2 LEF macros inside and can run simply using the good old ` flow tcl design` No need for interactive scripts please have a look at it it s much cleaner

aryap · Answer

ok i m trying this out now just to confirm you don t set ` env SYNTH READ BLACKBOX LIB ` and you don t provide `set env VERILOG FILES BLACKBOX `

Amr Gouhar · Answer

The black box is defined inside the same source file <https github com efabless openlane blob develop designs manual macro placement test src design v>

aryap · Answer

oooooh

aryap · Answer

well it worked

aryap · Answer

i m not sure what was different but it worked thank you

Wajeh ul hasan · Answer

< Amr Gouhar> I am also trying to place macros I saw this post and followed the instructions In my case the process gives error when doing detailed placement `non group cell region assign done ` ` ` `can t insert center cell ` `cell name imem` `can t insert center cell ` `cell name dmem` `non group cell placement done ` ` ` `Reading openLANE flow designs wajeh experiment runs floorplan tmp placement replace def is Done` `DEF file write success ` what does `can t insert center cell ` means here

Amr Gouhar · Answer

< Wajeh ul hasan> did you try running it directly from flow tcl without an interactive script following the example < Ahmed Ghazy> mentioned above

aryap · Answer

< Wajeh ul hasan> I ran into that if i hadn t made enough room in the floorplan try tweaking FP CORE UTIL and PL TARGET DENSITY

Wajeh ul hasan · Answer

< Amr Gouhar> Yes I did and it worked for the other design I guess it is as < aryap> has pointed out area issue Though I am curious are ` env MACRO PLACEMENT CFG ` and the command `add macro placement` alternative of each other If I use ` env MACRO PLACEMENT CFG ` then I dont see any point in using `add macro placement` and vice versa right

Amr Gouhar · Answer

< Wajeh ul hasan> Yes `add macro placement` creates this ` env MACRO PLACEMENT CFG ` that is then used by `manual macro placement` command We re currently trying to remove the need for interactive scripts at least up to the core level of a chip so this was one way to remove the reliance on the `add macro placement` command