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i still haven't managed to successfully place a macro and route around it. i have played with all manner of sizings, `FP_CORE_UTIL`, `PL_TARGET_DENSITY`, making sure to keep the die area larger than the placed macros. either `replace` fails because `decrease init_density_penalty` or I get to the end of the flow and the antenna placement fails. I have to run <https://github.com/growly/openlane/blob/develop/designs/250/tile.tcl|the custom script suggested> to make any progress. interestingly, even without manually placing the macro, i can get to the end of the flow and run into the same antenna failures in `or_diodes.tcl`

i can't see what is materially different about the caravel `mgmt_core/config.tcl` to suggest doing it that way

<@U01837QU37V>: As far as I know antenna insertion &amp; checking doesn't work on the top level (by top level I mean a design where only macros exist (no std cells)), so you'll have to skip these steps (don't include them in your interactive script) for now.
<@U016HSALFAN>: correct me, if I'm wrong.

<@U01837QU37V>, <@U01634FSETZ>: Antenna insertion works, but checking needs antenna information the LEFs.

<@U01837QU37V>: There is an example on develop now at <https://github.com/efabless/openlane/tree/develop/designs/manual_macro_placement_test> That has 2 LEF macros inside and can run simply using the good old `./flow.tcl -design`. No need for interactive scripts, please have a look at it; it's much cleaner.

ok i'm trying this out now - just to confirm, you don't set `::env(SYNTH_READ_BLACKBOX_LIB)`? and you don't provide `set ::env(VERILOG_FILES_BLACKBOX)`?

The black-box is defined inside the same source file <https://github.com/efabless/openlane/blob/develop/designs/manual_macro_placement_test/src/design.v>

i'm not sure what was different? but it worked! thank you!

<@U01634FSETZ> I am also trying to place macros. I saw this post and followed the instructions.
In my case the process gives error when doing detailed placement:
`non_group_cell_region_assign done ..`
 `- - - - - - - - - - - - - - - - - - - - - - - -` 
 `can't insert center cell !!` 
 `cell_name : imem`
 `can't insert center cell !!` 
 `cell_name : dmem`
 `non_group_cell_placement done ..` 
 `- - - - - - - - - - - - - - - - - - - - - - - -` 
`Reading /openLANE_flow/designs/wajeh_experiment/runs/floorplan/tmp/placement/replace.def is Done`
 `DEF file write success !!` 
what does `can't insert center cell !!`   means here?

<@U016Y9FMA2Y>: did you try running it directly from flow.tcl without an interactive script, following the example <@U016HSALFAN> mentioned above?

<@U016Y9FMA2Y> I ran into that if i hadn't made enough room in the floorplan. try tweaking FP_CORE_UTIL and PL_TARGET_DENSITY?

<@U01634FSETZ> Yes I did and it worked for the other design. I guess it is as <@U01837QU37V> has pointed out, area issue. Though I am curious, are `::env(MACRO_PLACEMENT_CFG)`  and the command `add_macro_placement` alternative of each other. If I use `::env(MACRO_PLACEMENT_CFG)` then I dont see any point in using `add_macro_placement` and vice versa, right?

<@U016Y9FMA2Y>: Yes, `add_macro_placement` creates this `::env(MACRO_PLACEMENT_CFG)` that is then used by `manual_macro_placement` command. We're currently trying to remove the need for interactive scripts (at least up to the core level of a chip), so this was one way to remove the reliance on the `add_macro_placement`  command.