Hello! How would one get a sky130 full adder prope...
# openlane
Hello! How would one get a sky130 full adder properly synthesized if directly instantiated within a verilog src file? I currently have a
module instantiated in a verilog file and it works with Verilator, but when trying to synthesize Openlane is having trouble finding the module. I've also tried to include
as both Verilog or Blackbox verilog files within
, but I end up getting a syntax error in another file (error in thread to keep this short). Is there a proper way to get this working? (Note: I am using rc2)
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2. Executing Verilog-2005 frontend: /home/anson/cs250_pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fa/sky130_fd_sc_hd__fa.behavioral.pp.v
/home/anson/cs250_pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fa/../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v:38: ERROR: syntax error, unexpected TOK_ID
[ERROR]: during executing: "yosys -c /openLANE_flow/scripts//synth.tcl -l /openLANE_flow/designs/mac_cluster/runs/12-11_02-15//logs/synthesis/yosys.log |& tee >&@stdout"
[ERROR]: Last 10 lines:
child process exited abnormally

[ERROR]: Please check yosys  log file
[ERROR]: Dumping to /openLANE_flow/designs/mac_cluster/runs/12-11_02-15//error.log
@Anson: You'll need to add it as a black-box in the source code. This is one example. Hint: no `include "`skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fa/*.v`" is needed.
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Thanks! It turns out that I was just missing the
config in my design
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Ah ignore the previous message. It was fixed after removing the faulty
statement! The config shouldn't have changed anything since it doesn't relate to synth module finding etc.
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