Hello! I have a design that no longer passes synth...
# openlane
Hello! I have a design that no longer passes synth when I update Openlane from
(no other changes). Is this expected? The error that I get is:
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[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
tns -22780.94
wns -154.24
[ERROR]: during executing: "sta /openLANE_flow/scripts/sta.tcl |& tee >&@stdout /openLANE_flow/designs/mac_cluster/runs/15-11_00-11/logs/synthesis/opensta.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child killed: segmentation violation

[ERROR]: Please check sta  log file
[ERROR]: Dumping to /openLANE_flow/designs/mac_cluster/runs/15-11_00-11/error.log
As an aside, the last time I got this error was when I first instantiated a SKY130 full adder cell without the proper config params, and the resolution was to increase the SYNTH_MAX_FANOUT. Could it be something similar with the config? I posted the config in the thread for reference.
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# User config
set ::env(DESIGN_NAME) mac_cluster

# Change if needed
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]

# Fill this
set ::env(CLOCK_PERIOD) "10"
set ::env(CLOCK_PORT) "clk"

set ::env(SYNTH_MAX_FANOUT) 7
set ::env(PL_TARGET_DENSITY) 0.35

set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
        source $filename
@Anson: it's the first time for me to encounter this strange behavior. OpenSTA has been mostly stable for the past months. However, can you try increasing the CLOCK_PERIOD to something like "164". Also, make sure that the CLOCK_PORT name is correct. If the issue persists, please open an issue on the OpenLANE repo.
Hi @Amr Gouhar, thanks for the help! The issue still persists after the fixes so I've opened up an issue here.