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What is the process creating `/results/floorplan/m...
# openlane
t
What is the process creating 
/results/floorplan/mydesign.floorplan.def
?
a
i think a few steps modify this file?
t
Yeah that's possible. I'm looking specifically for the first one (I think ) that creates all the 
ROWS
I'm looking in the scripts and it's not clear at all ... there is no mention of 
.floorplan.def
anywhere 🤷‍♂️
a
i'm looking in scripts/tcl_commands/floorplan.tcl. it defines various DEF files to work on. it also invokes bunch of other scripts
replace is the placement tool and it definitely writes it, but it also reads it first
a
@tnt: The first one is 
init_floorplan
.
t
Yeah looks like 
verilog2def
is the first thing creating the rows.
So to provide some context, I have 3 macros on the top of the chip that take significant amount of space. And I want to have all the std cell logic below them. Now if the space between those macros and the border and between themselves, I found that the 
.placement.def
"filtered out" the 
ROW
entries. which is pretty much what I want. And I was trying to figure out where this happens. Seems it's actuallyt the tapdecap step doing it.
output of 
RePlace
has 200 rows (originally created by verilog2def), then down to 25 after 
tapdecap
.
a
@Sylvain Munau Oh I see. Yes, tap_decap cuts the rows around macros by the distances defined by the HALOS (see this: https://github.com/efabless/openlane/blob/master/configuration/floorplan.tcl#L44)
@tnt * ^
t
Ok ! Great, that's exactly what I've been looking for, trying to figure out the criteria that was used !
Because until now I've been trying random values to get varied results ...
a
Whoops... Is it that tight on your block though?
@tnt: Also, regarding powering your macros, if they expose at least two long enough power vertical stripes on metal4, 
gen_pdn
should automatically hook those to the external met5 horizontal stripes.
t
a
I saw you're trying to use multiple OpenRAM blocks? Maybe see https://github.com/VLSIDA/OpenRAM/issues/98 for context on their power-routability.
t

https://i.imgur.com/lhIdC7G.png▾

a
That looks nice! Are you using the original LEFs output by the compiler for routing?
t
So picture for context. I wanted to space the macros horizontally a bit to leave more space for routing. But if I left too much space, it would start to put cells in there (and failing at placing them legally ...), hence why I was looking for the halo and the criteria used 🙂
👍 1
So for the SRAM I used the LEF from the caravel, except I added an obstruction on 
met5
so the router wouldn't route across them.
a
@tnt: Ah, I see. Should be able to automatically power-route to it then.
t
So the two main issues I have to solve first (I think) are : • Power routing to the macros :

https://i.imgur.com/lHOnKnX.png▾

The PDN grid • Diode Insertion happening outside the grid :

https://i.imgur.com/Oi5zerz.png▾

There is nothing there, no connection to pwr/gnd or no n-well so ... doesn't work.
a
Hm, the out-of-area diode insertion by FR should've been fixed in the latest openroad app, but I suppose you're already using that?
t
I updated OpenRoad to match the latest commit id you use in the 
develop
branch.
70f7b682b3c381bd9b6e4466017dbac46fa71d9f
a
Does the same happen with DIODE_INSERTION_STRATEGY == 1?
t
Let me try.
(btw, turned out that commit id is 
master
of openroad ...)
a
https://github.com/efabless/caravel/tree/release/openlane/storage Does something very similar to what you have with 
set ::env(DIODE_INSERTION_STRATEGY) 1
. Maybe check out the configs.
t
Ok, so with strategy 
1
I indeed don't get those diodes in the middle of nowhere 👍 Routing didn't finish without violations, so I'll need to tweak stuff but that I can probably figure out by myself. Tx. I tried the other strategy yeterday (before I had updated OpenLane and OpenRoad) and they both failed, I guess I should have retried after the update.
👏 1
Now I need to workout how to route power. I guess I can't manually extend those two wide stripe outside the macro area so they intersect with the PDN network 😅
😕
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