<@U016HSALFAN> has helped me get a logo placed. St...
# openlane
@User has helped me get a logo placed. Still needs work... https://github.com/mattvenn/openlane-logo-test/pulls
✔️ 1
That looks fairly large, that's going to interrupt your PDN right ? Also with metal density rules, wouldnt a lot of the area get re-filled ?
Mm, I might be misreading the scale actually. This sqaure is the whole user area ?
No, 20 um
So 800um x 800um
Pretty big
I was wondering if it'd be possible to draw something by modulating the width of the PDN grid straps.
😮 1
Now that is a cool idea
Heard of Norwegian pixel?
But yeah after looking it up, exactly what I had in mind 😅
Just small hint, It's often OK to put a logo only on the top metal layer. Logos on lower layers only make sense when doing (SEM) inspection during production or if one plans to decapsulate the chip. GIven the WLCSP planned I am not even sure if logo on top metal will be visible.
yes, this is on metal 5
I've had a chat with zeptobars and John McMaster and they're both happy to decap a few samples