https://open-source-silicon.dev logo
#openlane
Title
# openlane
a

aryap

11/28/2020, 12:21 AM
if we're hardening a macro to place within the die, can we just skip io placement? i'm getting errors about the number of pins that can fit around the permiter of the design, but i don't want it to matter
t

tnt

11/28/2020, 6:36 AM
You can look at what I do in https://github.com/PyFive-RISC-V/pyfive_top_202011 I don't skip IO placement but in my macro I only fixed the pins that I actually use. Then I wire those to the right pin in the
user_project_wrapper
. Note that because inside the wrapper I don't have any standard cells, I cannot wire stuff to even
1
or
0
(because those use standard cells to output constans, the
conb
bloks) ... so I added ports in my macro that output constant signals so I wire unused stuff in the
wrapper
to them.
🎉 1
a

aryap

11/30/2020, 1:01 AM
ok, i couldn't solve all my problems so i tried folding more of the logic into the child macros. now i'm trying to place 3 macros and 4 tie high/low cells. this is nightmarishly difficult for such a trivial task.
what do you mean you don't have standard cells in pyfive_top? i see sky130_fd_sc_hd__buf_8 etc?
t

tnt

11/30/2020, 7:06 AM
I don't have standard cell in the
user_project_wrapper
. I of course have cells in my
pyfive_top
block.
And the issue you're having is exactly why I avoided any cells in the
user_project_wrapper
I didn't want to have to go through all the steps of having a grid and placement etc ... for just a few tie cells.
So instead I had my
pyfive_top
macro output a constant zero and a constant one on a couple of pins and I connect to that instad of
1b1
or
1b0
in the
user_project_wrapper
if I want to tie anything high/low.
👌 2
a

aryap

11/30/2020, 8:08 PM
ok, i gotchu. my solution seems to be to re-run the flow until the initial seed places the 4 annoying cells somewhere not problematic
quality. of. result.
2 Views