open-source-silicon.dev

yosys only supports a sub-set of System Verilog and you might also need to enable it with `-sv` flag to the `read_verilog` command for it to work at all.

Thanks for the quick response I will take a look at which point this is being called and add the flag to test if it resolves my issue. Thanks!!

FYI. The "-sv" solved some of the issues but unfortunately it does not support structs. I made use of an external tool to translate system verilog to verilog. Now the _yosys_ run goes through several steps before reporting a new error after flatten design (21.3)