Thanks for the information given that the exa

Question

< U016HSAH6AE> Thanks for the information given that the example run shows the same and finishes I see that the openroad problem is just a print and the execution can continue In case unexpected REG messages are a bug in the openROAD Verilog frontend then I may have to wait until it is fixed Unfortunately the deadline finishes today which worries me a bit < U019HVBG2JX> I am trying to integrate a custom core so there are a lot of registers to save the information and state over the pipeline Looking at the user proj example v file caravel verilog rtl user proj example v I can see reg signals on the counter module and the flow works as expected < U016HU5HK8V> I added a wrapper for my core within the `user project wrapper` verilog file so there are no signals declared at the top level the I O ports are directly connected to my core wrapper instance Then I modified the config tcl file openlane user project wrapper config tcl adding the verilog files for my project and commenting out some variables of the given config file currently it looks like shown in the thread comment

Joel Sanchez · Answer

<http confic tt|confic tcl file> looks like ```set script dir file dirname file normalize info script set env DESIGN NAME user project wrapper set env FP PIN ORDER CFG $script dir pin order cfg set env PDN CFG $script dir pdn tcl set env FP PDN CORE RING 1 set env FP SIZING absolute set env DIE AREA 0 0 2920 3520 set unit 2 4 set env FP IO VEXTEND expr 2 $ unit set env FP IO HEXTEND expr 2 $ unit set env FP IO VLENGTH $ unit set env FP IO HLENGTH $ unit set env FP IO VTHICKNESS MULT 4 set env FP IO HTHICKNESS MULT 4 set env CLOCK PORT user clock2 set env CLOCK NET core wrapper wb clk i set env CLOCK PERIOD 10 set env PL OPENPHYSYN OPTIMIZATIONS 0 set env DIODE INSERTION STRATEGY 0 Need to fix a FastRoute bug for this to work but it s good for a sense of isolation set env MAGIC ZEROIZE ORIGIN 0 set env MAGIC WRITE FULL LEF 1 set env DESIGN IS CORE 0 set env PL BASIC PLACEMENT 1 set env PL TARGET DENSITY 0 15 set env VERILOG FILES $script dir verilog rtl defines v $script dir verilog rtl custom core alu top v $script dir verilog rtl custom core mul stage v $script dir verilog rtl custom core mul top v $script dir verilog rtl custom core tlb cache v $script dir verilog rtl custom core cache lru v $script dir verilog rtl custom core cache top v $script dir verilog rtl custom core store buffer v $script dir verilog rtl custom core data cache v $script dir verilog rtl custom core regFile v $script dir verilog rtl custom core decode top v $script dir verilog rtl custom core core top v $script dir verilog rtl custom core writeback xcpt v $script dir verilog rtl custom core reorder buffer v $script dir verilog rtl custom core wb top v $script dir verilog rtl custom core fetch top v $script dir verilog rtl custom core instruction cache v $script dir verilog rtl custom core core top wrapper v $script dir verilog rtl user project wrapper v ```