open-source-silicon.dev

<@U016HSAH6AE> Thanks for the information, given that the example run shows the same and finishes I see that the /.openroad problem is just a print and the execution can continue. In case "unexpected REG" messages are a bug in the openROAD Verilog frontend then I may have to wait until it is fixed. Unfortunately, the deadline finishes today which worries me a bit.

<@U019HVBG2JX> I am trying to integrate a custom core, so there are a lot of registers to save the information and state over the pipeline. Looking at the _user_proj_example.v_ file (caravel/verilog/rtl/user_proj_example.v) I can see _reg_ signals on the counter module and the flow works as expected.

<@U016HU5HK8V> I added a wrapper for my core within the `user_project_wrapper` verilog file, so there are no signals declared at the top level, the I/O ports are directly connected to my core wrapper instance. Then, I modified the config.tcl file (openlane/user_project/wrapper/config.tcl)  adding the verilog files for my project and commenting out some variables of the given config file, currently it looks like shown in the thread comment.

<http://confic.tt|confic.tcl file> looks like:

```set script_dir [file dirname [file normalize [info script]]]

set ::env(DESIGN_NAME) user_project_wrapper
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg

#set ::env(PDN_CFG) $script_dir/pdn.tcl
#set ::env(FP_PDN_CORE_RING) 1
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 2920 3520"

#set ::unit 2.4
#set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
#set ::env(FP_IO_HEXTEND) [expr 2*$::unit]
#set ::env(FP_IO_VLENGTH) $::unit
#set ::env(FP_IO_HLENGTH) $::unit
#
#set ::env(FP_IO_VTHICKNESS_MULT) 4
#set ::env(FP_IO_HTHICKNESS_MULT) 4



set ::env(CLOCK_PORT) "user_clock2"
set ::env(CLOCK_NET) "core_wrapper.wb_clk_i"

set ::env(CLOCK_PERIOD) "10"

#set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
#set ::env(DIODE_INSERTION_STRATEGY) 0

# Need to fix a FastRoute bug for this to work, but it's good
# for a sense of "isolation"
#set ::env(MAGIC_ZEROIZE_ORIGIN) 0
#set ::env(MAGIC_WRITE_FULL_LEF) 1

set ::env(DESIGN_IS_CORE) 0
set ::env(PL_BASIC_PLACEMENT) 1
set ::env(PL_TARGET_DENSITY) 0.15

set ::env(VERILOG_FILES) "\
	$script_dir/../../verilog/rtl/defines.v \
    $script_dir/../../verilog/rtl/custom_core/alu_top.v \
    $script_dir/../../verilog/rtl/custom_core/mul_stage.v \
    $script_dir/../../verilog/rtl/custom_core/mul_top.v \
    $script_dir/../../verilog/rtl/custom_core/tlb_cache.v \
    $script_dir/../../verilog/rtl/custom_core/cache_lru.v \
    $script_dir/../../verilog/rtl/custom_core/cache_top.v \
    $script_dir/../../verilog/rtl/custom_core/store_buffer.v \
    $script_dir/../../verilog/rtl/custom_core/data_cache.v \
    $script_dir/../../verilog/rtl/custom_core/regFile.v \
    $script_dir/../../verilog/rtl/custom_core/decode_top.v \
    $script_dir/../../verilog/rtl/custom_core/core_top.v \
    $script_dir/../../verilog/rtl/custom_core/writeback_xcpt.v \
    $script_dir/../../verilog/rtl/custom_core/reorder_buffer.v \
    $script_dir/../../verilog/rtl/custom_core/wb_top.v \
    $script_dir/../../verilog/rtl/custom_core/fetch_top.v \
    $script_dir/../../verilog/rtl/custom_core/instruction_cache.v \
	$script_dir/../../verilog/rtl/custom_core/core_top_wrapper.v \
	$script_dir/../../verilog/rtl/user_project_wrapper.v "```
