open-source-silicon.dev

has anyone hit an out-of-memory bug with netgen? doing lvs, `netgen -batch lvs`, it consumes 200 GB of ram and gets killed

Trying to remember what it was and how I solved it, gimme a second ...

Do you see a bunch of :
```Warning:  Cell sky130_fd_sc_hd__decap_8 has no pins
Note:  Implicit pin (no pins)```

is it an LVS output? i'll re-run the flow

you can just re-run the LVS step on teh existing run.

i'd already blown it away when i reran the script

(i just turned LVS off and lo and behold, no problem :laughing:)

If you don't test, you can't fail :smile:

in any case, how did you solve that problem?

actually IIRC I did see that error, now that i think of it, and i thought no problem why does the decap need pins. it's probably connected somewhere along the row

That problem originated from my custom build and `write_powered_verilog` not being called as a result.

oh i see,
```	if { $::env(DIODE_INSERTION_STRATEGY) == 2 } {
		run_antenna_check
		heal_antenna_violators; # modifies the routed DEF
	}

    if { $::env(LVS_INSERT_POWER_PINS) } {
		write_powered_verilog
		set_netlist $::env(lvs_result_file_tag).powered.v
    }```
appears in the non-interactive set of commands in `flow.tcl` but not the interactive one

i'll try this. thanks <@U016HU5HK8V> :pray:

Yeah at some point in openlane that little bit of code got moved from inside some function into the top level `flow.tcl` ... and so I needed to update my `interactive.tcl` accordingly ...