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#openlane
Title
a
aryap
11/30/2020, 7:29 PMhas anyone hit an out-of-memory bug with netgen? doing lvs,
netgen -batch lvst
tnt
11/30/2020, 7:32 PMYes ...
Trying to remember what it was and how I solved it, gimme a second ...
Do you see a bunch of :
Copy code
Warning: Cell sky130_fd_sc_hd__decap_8 has no pins
Note: Implicit pin (no pins)?
a
aryap
11/30/2020, 7:55 PMlet me see
is it an LVS output? i'll re-run the flow
t
tnt
11/30/2020, 7:56 PMYeah it's from LVS.
you can just re-run the LVS step on teh existing run.
or look at the .log
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aryap
11/30/2020, 7:58 PMi'd already blown it away when i reran the script
(i just turned LVS off and lo and behold, no problem 😆)
t
tnt
11/30/2020, 7:59 PMIf you don't test, you can't fail 😄
🔥 1
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aryap
11/30/2020, 8:02 PMin any case, how did you solve that problem?
actually IIRC I did see that error, now that i think of it, and i thought no problem why does the decap need pins. it's probably connected somewhere along the row
t
tnt
11/30/2020, 8:03 PMThat problem originated from my custom build and
write_powered_veriloga
aryap
11/30/2020, 8:03 PMchecks
oh i see,
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if { $::env(DIODE_INSERTION_STRATEGY) == 2 } {
run_antenna_check
heal_antenna_violators; # modifies the routed DEF
}
if { $::env(LVS_INSERT_POWER_PINS) } {
write_powered_verilog
set_netlist $::env(lvs_result_file_tag).powered.v
}flow.tclwhich i also copied like you, i guess
i'll try this. thanks @tnt 🙏
t
tnt
11/30/2020, 8:07 PMYeah at some point in openlane that little bit of code got moved from inside some function into the top level
flow.tclinteractive.tcla
aryap
11/30/2020, 8:37 PMthat fixed it! 🙏 🙏 🙏
👍 1