drr
12/01/2020, 7:06 AMb427e3bd10dcdc36891ae270a1ef0bd02602c553
)
https://gist.github.com/dan-rodrigues/6673cffcd67fce661ffee6f322ac9eb1
are people seeing these warnings and it just works as normal? missing power connections seems like a show stoppertnt
12/01/2020, 7:15 AM.log
file they appeat in the run
repo, I can check here ... if I have themdrr
12/01/2020, 7:17 AMopensta_post_openphysyn.log
tnt
12/01/2020, 7:17 AM6547ee36754cd8e6aa0eb2de07ee10ad7e0c06e8
) or openlane ( 817314be3c7996f62b6cb499e35e2107d4b822e2
) either.drr
12/01/2020, 7:17 AM6547ee36754cd8e6aa0eb2de07ee10ad7e0c06e8
tnt
12/01/2020, 7:18 AMOpenSTA 2.2.0 b0f0de488f Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 <<http://gnu.org/licenses/gpl.html>>
This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details.
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Error: cannot open '/home/tnt/.sta'.
Warning: /home/tnt/sky130/openlane_workspace/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /home/tnt/sky130/openlane_workspace/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /home/tnt/sky130/openlane_workspace/openlane/designs/pyfive_top/runs/golden_pwr/results/synthesis/pyfive_top.synthesis_optimized.v, line 37048 module sram_1rw1r_32_256_8_sky130 not found. Creating black box for \audio_I.fifo_I.ram_I .
Warning: /home/tnt/sky130/openlane_workspace/openlane/designs/pyfive_top/runs/golden_pwr/results/synthesis/pyfive_top.synthesis_optimized.v, line 38516 module sky130_fd_sc_hd__tapvpwrvgnd_1 not found. Creating black box for PHY_252.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 3.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 3.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load $cap_load [all_outputs]
tns 0.00
wns 0.00
drr
12/01/2020, 7:19 AMtnt
12/01/2020, 7:20 AMf1d096dac23d8c403296f0731be57fb0a7bb652a
VPWR
/ VGND
in my pyfive_top.synthesis_optimized.v
aryap
12/01/2020, 7:22 AMmake install
have you?drr
12/01/2020, 7:22 AMca58d58c07ab2dac53488df393da633fd5fb9a02
so I'll try again with yoursaryap
12/01/2020, 7:22 AMopen_pdks
generates sky130A
it hardcodes the paths to your skywater-pdk
dir... i hit that early on)drr
12/01/2020, 7:25 AMtnt
12/01/2020, 7:25 AM<https://github.com/dan-rodrigues/caravel-vdp-lite/>
up to date ?drr
12/01/2020, 7:27 AMMagic 8.3 revision 87 - Compiled on Mon Nov 23 17:53:03 UTC 2020.
magic is involved in the open_pdks setup, here's what I got from the included docker image in openlanemake vdp_lite_user_proj
tnt
12/01/2020, 7:31 AMdrr
12/01/2020, 7:33 AM$readmemh
file since AFAIK Yosys just checks the cwd when searchingtnt
12/01/2020, 7:34 AMflow.tcl
in my install directly./opensta_spef.log
step herexxx.synthesis_preroute.v
file, the cells don't have the VPWR
/ VGND
/ VPB
/ VNB
ports for me.drr
12/01/2020, 8:21 AMWarning: /project/openlane/vdp_lite_user_proj/runs/01-12_06-34/results/synthesis/vdp_lite_user_proj.synthesis_optimized.v, line 54 instance _19673_ port VGND not found.
logs?opensta_post_openphysyn.log
)tnt
12/01/2020, 8:31 AMsynthesis_optimized
verilog (for the vdp project) doesn't have the VPWR/VGND ports.drr
12/01/2020, 8:35 AMmaster
, and ensuring openlane is the same as yours (think it was develop
)tnt
12/01/2020, 8:39 AMdrr
12/01/2020, 8:45 AMtnt
12/01/2020, 8:55 AMpdn.tcl
in my project so the one from open_pdk isn't used for me.drr
12/01/2020, 9:01 AMtnt
12/01/2020, 9:02 AMgen_pdn
call changed aswell which would require updating the interactive.tcl
which is one reason I'm not updating ATM, I don't want ot have to mess with that while it works.drr
12/01/2020, 9:02 AMmake ship
complete GDS I have is probably junk now anywaydevelop
for nowtnt
12/01/2020, 9:06 AMdevelop
that it changed, over the weekend 😅drr
12/01/2020, 9:07 AM817314be3c7996f62b6cb499e35e2107d4b822e2
Amr Gouhar
12/01/2020, 1:39 PMtnt
12/01/2020, 1:41 PMpdn.tcl
based on common_pdn.tcl
) and I didn't really notice any issue.set ::rails_mlayer "met1" ;
which has been removed recently too.Amr Gouhar
12/01/2020, 2:31 PMset ::rails_mlayer "met1" ;
was removed since we specify it anyways in the stdcell
section.tnt
12/01/2020, 3:23 PMAhmed Ghazy
12/07/2020, 4:47 PM