On the recent open pdks I can no longer build my design usin

Question

On the recent open pdks I can no longer build my design using openlane and there are new warnings which seem like fatal errors probably related I ve noticed missing VGND and VPWR warnings in the synthesis optimized v output of my user project when it comes to an OpenSTA step they did not appear in an older Nov 22 commit of open pdks `b427e3bd10dcdc36891ae270a1ef0bd02602c553` are people seeing these warnings and it just works as normal missing power connections seems like a show stopper

tnt · Answer

If you tell me in which ` log` file they appeat in the `run` repo I can check here if I have them

drr · Answer

Thanks it is in `opensta post openphysyn log`

drr · Answer

which should be in logs synthesis

tnt · Answer

Note that I m not on the latest open pdk `6547ee36754cd8e6aa0eb2de07ee10ad7e0c06e8` or openlane `817314be3c7996f62b6cb499e35e2107d4b822e2` either

drr · Answer

ah yeah forgot to say I got the same issue in `6547ee36754cd8e6aa0eb2de07ee10ad7e0c06e8`

tnt · Answer

```OpenSTA 2 2 0 b0f0de488f Copyright c 2019 Parallax Software Inc License GPLv3 GNU GPL version 3 lt <http gnu org licenses gpl html> gt This is free software and you are free to change and redistribute it under certain conditions type `show copying for details This program comes with ABSOLUTELY NO WARRANTY for details type `show warranty Error cannot open home tnt sta Warning home tnt sky130 openlane workspace pdks sky130A libs ref sky130 fd sc hd lib sky130 fd sc hd ff n40C 1v95 lib line 31 default operating condition ff n40C 1v95 not found Warning home tnt sky130 openlane workspace pdks sky130A libs ref sky130 fd sc hd lib sky130 fd sc hd ss 100C 1v60 lib line 32 default operating condition ss 100C 1v60 not found Warning home tnt sky130 openlane workspace openlane designs pyfive top runs golden pwr results synthesis pyfive top synthesis optimized v line 37048 module sram 1rw1r 32 256 8 sky130 not found Creating black box for audio I fifo I ram I Warning home tnt sky130 openlane workspace openlane designs pyfive top runs golden pwr results synthesis pyfive top synthesis optimized v line 38516 module sky130 fd sc hd tapvpwrvgnd 1 not found Creating black box for PHY 252 create clock get ports $ env CLOCK PORT name $ env CLOCK PORT period $ env CLOCK PERIOD set input delay value expr $ env CLOCK PERIOD $ env IO PCT set output delay value expr $ env CLOCK PERIOD $ env IO PCT puts INFO Setting output delay to $output delay value INFO Setting output delay to 3 0 puts INFO Setting input delay to $input delay value INFO Setting input delay to 3 0 set clk indx lsearch all inputs get port $ env CLOCK PORT set rst indx lsearch all inputs get port resetn set all inputs wo clk lreplace all inputs $clk indx $clk indx set all inputs wo clk rst lreplace $all inputs wo clk $rst indx $rst indx set all inputs wo clk rst $all inputs wo clk correct resetn set input delay $input delay value clock get clocks $ env CLOCK PORT $all inputs wo clk rst set input delay 0 0 clock get clocks $ env CLOCK PORT resetn set output delay $output delay value clock get clocks $ env CLOCK PORT all outputs TODO set this as parameter set driving cell lib cell $ env SYNTH DRIVING CELL pin $ env SYNTH DRIVING CELL PIN all inputs set cap load expr $ env SYNTH CAP LOAD 1000 0 puts INFO Setting load to $cap load INFO Setting load to 0 01765 set load $cap load all outputs tns 0 00 wns 0 00```

drr · Answer

huh ok no VPWR GND warnings I think the open pdks make install blows away the sky130A dir before copying so not sure if anything bad is leftover

drr · Answer

can you share your skywater pdks commit you used

drr · Answer

not sure what else to check

tnt · Answer

`f1d096dac23d8c403296f0731be57fb0a7bb652a`

tnt · Answer

There are no mention of `VPWR` `VGND` in my `pyfive top synthesis optimized v`

tnt · Answer

which AFAIK is expected at that stage

aryap · Answer

dumb question you haven t moved the dir after `make install` have you

drr · Answer

hm I m at `ca58d58c07ab2dac53488df393da633fd5fb9a02` so I ll try again with yours

aryap · Answer

when `open pdks` generates `sky130A` it hardcodes the paths to your `skywater pdk` dir i hit that early on

drr · Answer

that said I don t see much change apart from some build system stuff

drr · Answer

yeah I ve kept it in the same sky130A dir I ve run into that issue before too

tnt · Answer

Yeah I doubt the PDK version would make any difference

tnt · Answer

Is `<https github com dan rodrigues caravel vdp lite >` up to date

drr · Answer

`Magic 8 3 revision 87 Compiled on Mon Nov 23 17 53 03 UTC 2020 ` magic is involved in the open pdks setup here s what I got from the included docker image in openlane

drr · Answer

just checking now

drr · Answer

Yes that should be the config that produces that included GDS LEF after `make vdp lite user proj`

drr · Answer

it looks up to date

tnt · Answer

err reduce hex not found

tnt · Answer

Oh it wants it in th cwd that s weird

drr · Answer

there s a symlink in openlane to it I d like a neater way to specify the `$readmemh` file since AFAIK Yosys just checks the cwd when searching

drr · Answer

if I run make form openlane it works here and seems to pick up the symlink in that dir

tnt · Answer

yeah I don t run with docker so I was calling `flow tcl` in my install directly

tnt · Answer

Started gotta run an errand for 10 min we ll see results them

tnt · Answer

yeah it got OOM d

tnt · Answer

But it s in the ` opensta spef log` step here

tnt · Answer

looking at my `xxx synthesis preroute v` file the cells don t have the `VPWR` `VGND` `VPB` `VNB` ports for me

drr · Answer

I get the OOM too but weird that it s in a different step so you do not see the `Warning project openlane vdp lite user proj runs 01 12 06 34 results synthesis vdp lite user proj synthesis optimized v line 54 instance 19673 port VGND not found ` logs

drr · Answer

in `opensta post openphysyn log`

tnt · Answer

Mmm my `synthesis optimized` verilog for the vdp project doesn t have the VPWR VGND ports

tnt · Answer

So something is causing those to be added too early in the flow

drr · Answer

huh bizarre that the open pdks commit is the difference between it working and not working in that case

drr · Answer

I manually nuked sky130A myself and am doing another run from `master` and ensuring openlane is the same as yours think it was `develop`

tnt · Answer

did you look at the change log

drr · Answer

the most relevant thing I could spot is this <https github com RTimothyEdwards open pdks commit db8759823e490cc7031d124e3688a424cac26892 diff d1a4ecdae6460af432395e8a432df884a481e18fa3810c02a165bbac32272decR5> but I m not familiar with the systems involved here and can t really comment on how if why that would be related

drr · Answer

I wouldn t mind git bisecting it but the time spent would be absolutely killer

drr · Answer

hmm I do see some pdn changes in caravel which I haven t merged in <https github com efabless caravel commit 6aea300df81ca8fc276178670339fb74895413b8> I ll try merging latest caravel update my pdn cfg to match

tnt · Answer

Mmm interesting I do have a custom `pdn tcl` in my project so the one from open pdk isn t used for me

drr · Answer

yeah that might be part of my issue with the old pdn tcl

drr · Answer

I did notice that manually removing sky130A and doing open pdks make install got me past that with my old caravel design I won t rely on the script for that anymore did seem ok so far

tnt · Answer

I know in newer openlane the position of `gen pdn` call changed aswell which would require updating the `interactive tcl` which is one reason I m not updating ATM I don t want ot have to mess with that while it works

drr · Answer

but I should upgrade the caravel regardless DRC issues aside the `make ship` complete GDS I have is probably junk now anyway

drr · Answer

right that s good to know about openlane I m staying on `develop` for now

tnt · Answer

well it s on `develop` that it changed over the weekend sweat smile

tnt · Answer

but yeah I updated caravel to latest yesterday before doing the integration of everything

drr · Answer

my bad I confused the repo I was talking about

drr · Answer

openlane here is actually `817314be3c7996f62b6cb499e35e2107d4b822e2`

drr · Answer

which seems like a stable one

drr · Answer

ok I just scrolled to the rest of the thread I think we re on the same commit here

Amr Gouhar · Answer

< drr> Maybe this would answer your question It has been merged However I wouldn t recommend moving forward with the PDK version until we update it in either branches of either repos usually I run some tests first before updating the versions just to make sure everything will still be stable

tnt · Answer

< Amr Gouhar> I m actually wondering what that whole section in the pdn config does I mean I don t have it it wasn t there at all a week ago when I originally created my custom `pdn tcl` based on `common pdn tcl` and I didn t really notice any issue

tnt · Answer

I also have the `set rails mlayer met1 ` which has been removed recently too

Amr Gouhar · Answer

< tnt> What I know is that this section will add the instantiations of the power pins and their nets to the DEF and that they would be reflected in the DEF and the netlists from that point of the flow onward Unlike what we used to do which include them in the verilog after detailed routing and spef extraction However < Ahmed Ghazy> will probably be able to give a more detailed answer because I was unable to find the documentation for this section The `set rails mlayer met1 ` was removed since we specify it anyways in the `stdcell` section

Amr Gouhar · Answer

Thinking about it again now I guess I could ve gone with controlling the flag in this line <https github com efabless openlane blob ed1c59bdf7045c22c6c6ad64028daebee5947cdd scripts openroad or write verilog tcl L24> based on the flow stage to avoid this

tnt · Answer

At least this doesn t require the PDNGen patch which is required for the other way IIUC

Ahmed Ghazy · Answer

< tnt> I made the pdngen hack the default on develop until I or the OpenROAD guys deal with it in OpenDB