you can look at the DEF to see what it did that usually poin open-source-silicon #openlane

Channels

hdl21

unic-cass-23

events

pd-openlane-and-sky130

chipignite2206q_stanford_bringup

dynamic-power-estimation

fossee-iitb-google-sky130

coalition-for-digital-environmental-sustainability

vlsi101

magical

vlsi_verilog_using_opensource_eda

basebands

vlsi_verilog_using_opensoure_eda

digital-electronics-learners

open-microelectronics-textbook

mwcas-2023-rtl2silicon

system-verilog-learners

vlsi-learners-group

chilechipmakers

silicon-validation-private

openhighqualityresonators

opendataset-circuitnet-for-ml-tasks-in-vlsi-cad

generative-ai-silicon-challenge

community_denmark_dtu

Title

tnt

12/02/2020, 1:17 PM

you can look at the DEF to see what it did, that usually point me at what's going wrong.

Matt Venn

12/02/2020, 1:32 PM

how do you mean? which def?

tnt

12/02/2020, 1:33 PM

Whatever .DEF is fed to Replace at that stage.

the log should show what input it reads.

Matt Venn

12/02/2020, 1:34 PM

and which readme? I grepped openlane for fp_target_util but didn't come up with anything

tnt

12/02/2020, 1:34 PM

ah it's

FP_CORE_UTIL

PL_TARGET_DENSITY=(FP_CORE_UTIL+(1~5)/100).

Matt Venn

12/02/2020, 1:37 PM

thanks

I think I just have too many pins

with the mux separated, now I have to have 7 x io_in and io_out

so about 560 pins

to connect the macros

tnt

12/02/2020, 1:40 PM

Arf do you need all ios for all macros ?

Matt Venn

12/02/2020, 1:41 PM

but trying to keep it generic

so just exposing all the pins

in the previous version they would all get optimised out in synthesis