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`yosys_rewrite_verilog.tcl` is taking over 10 minu...
# openlane
a
yosys_rewrite_verilog.tcl
is taking over 10 minutes on my design. Is it just to get explicit wire definitions (the comments suggest it might be)? I wonder if OpenROAD could emit them when writing out the file, vs us having to rewrite it with yosys
a
@Anton Blanchard: As far as I recall, it was an issue with the netgen parser, but I tried out a couple of small designs without yosys rewriting verilog and it seems to be working now. I'll try out a larger test set and if the parser is still okay with this I'll remove this step/make it optional disabled by default.
@Anton Blanchard: I added the flag to disable this by default on develop, I tried it on a couple more designs and netgen isn't complaining about anything. So, you can try out the latest develop or apply this commit on your version of OpenLANE: https://github.com/efabless/openlane/commit/60a06b2e3a18c149cb4c13c8e5ae50eff7bfaa64 and let me know if anything went wrong with this.
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Thanks @Amr Gouhar, I'm not seeing any issues with my designs either.
I'm having trouble running gate level simulation on caravel, and I wonder if this is causing it:
Copy code
../../../../gl/user_project_wrapper.v:55: error: Net _05063_ is not defined in this context.
../../../../gl/user_project_wrapper.v:55: error: Output port expression must support continuous assignment.
../../../../gl/user_project_wrapper.v:55:      : Port 1 (Y) of sky130_fd_sc_hd__inv_2 is connected to _05063_
../../../../gl/user_project_wrapper.v:54: error: Unable to bind wire/reg/memory `microwatt_0.soc0.processor._01_[104]' in `minimal.uut.mprj'
Fixed it with 
default_nettype wire
a
@Anton Blanchard: Yeah, that's one down side of it, without wire declarations you'll need to add 
default_nettype wire
to simulate, however since this is an openlane generated netlist it's safe to assume that they would all be wires.
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