Anton Blanchard
01/15/2021, 2:31 AMyosys_rewrite_verilog.tcl
is taking over 10 minutes on my design. Is it just to get explicit wire definitions (the comments suggest it might be)? I wonder if OpenROAD could emit them when writing out the file, vs us having to rewrite it with yosysAmr Gouhar
01/15/2021, 5:58 PMAnton Blanchard
01/16/2021, 7:28 PM../../../../gl/user_project_wrapper.v:55: error: Net _05063_ is not defined in this context.
../../../../gl/user_project_wrapper.v:55: error: Output port expression must support continuous assignment.
../../../../gl/user_project_wrapper.v:55: : Port 1 (Y) of sky130_fd_sc_hd__inv_2 is connected to _05063_
../../../../gl/user_project_wrapper.v:54: error: Unable to bind wire/reg/memory `microwatt_0.soc0.processor._01_[104]' in `minimal.uut.mprj'
default_nettype wire
Amr Gouhar
01/20/2021, 1:04 PMdefault_nettype wire
to simulate, however since this is an openlane generated netlist it's safe to assume that they would all be wires.