`yosys rewrite verilog tcl` is taking over 10 minutes on my

Question

`yosys rewrite verilog tcl` is taking over 10 minutes on my design Is it just to get explicit wire definitions the comments suggest it might be I wonder if OpenROAD could emit them when writing out the file vs us having to rewrite it with yosys

Amr Gouhar · Answer

< Anton Blanchard> As far as I recall it was an issue with the netgen parser but I tried out a couple of small designs without yosys rewriting verilog and it seems to be working now I ll try out a larger test set and if the parser is still okay with this I ll remove this step make it optional disabled by default

Amr Gouhar · Answer

< Anton Blanchard> I added the flag to disable this by default on develop I tried it on a couple more designs and netgen isn t complaining about anything So you can try out the latest develop or apply this commit on your version of OpenLANE and let me know if anything went wrong with this

Anton Blanchard · Answer

Thanks < Amr Gouhar> I m not seeing any issues with my designs either

Anton Blanchard · Answer

I m having trouble running gate level simulation on caravel and I wonder if this is causing it ``` gl user project wrapper v 55 error Net 05063 is not defined in this context gl user project wrapper v 55 error Output port expression must support continuous assignment gl user project wrapper v 55 Port 1 Y of sky130 fd sc hd inv 2 is connected to 05063 gl user project wrapper v 54 error Unable to bind wire reg memory `microwatt 0 soc0 processor 01 104 in `minimal uut mprj ```

Anton Blanchard · Answer

Fixed it with `default nettype wire`

Amr Gouhar · Answer

< Anton Blanchard> Yeah that s one down side of it without wire declarations you ll need to add `default nettype wire` to simulate however since this is an openlane generated netlist it s safe to assume that they would all be wires