@User @User I noticed the caravel version of DFFRAM has power hooked up, but the original version from the DFFRAM repo doesn't. Looking at the gate level verilog, it does seems like openlane hooked up the standard cells correctly, but is that a good idea? Basically I'm trying to decide if I should submit this as a PR to DFFRAM: https://github.com/antonblanchard/DFFRAM/commit/eb793fd041b6d65482711839a5ef58e8fbdfa188

openlane always creates those "default" power connections, yes. In my opinion, it's usually good to be explicit, so I would say just submit the PR and wait for Prof. Shalan's opinion.

Thanks @Ahmed Ghazy