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#openlane
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# openlane
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Anton Blanchard

01/20/2021, 11:06 AM
@User @User I noticed the caravel version of DFFRAM has power hooked up, but the original version from the DFFRAM repo doesn't. Looking at the gate level verilog, it does seems like openlane hooked up the standard cells correctly, but is that a good idea? Basically I'm trying to decide if I should submit this as a PR to DFFRAM: https://github.com/antonblanchard/DFFRAM/commit/eb793fd041b6d65482711839a5ef58e8fbdfa188
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Ahmed Ghazy

01/20/2021, 12:51 PM
openlane always creates those "default" power connections, yes. In my opinion, it's usually good to be explicit, so I would say just submit the PR and wait for Prof. Shalan's opinion.
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Anton Blanchard

01/20/2021, 7:21 PM
Thanks @Ahmed Ghazy