Hi, Could anyone please tell why I am getting so much large delay for the highlighted cell in the below attached timing report? It is occurring in the reset path of flops. If it is due to high fanout then how I can handle this issue? I have synthesized the design in Openlane using yosys and performed STA using openSTA. Thanking you in anticipation.

Hi, @Ayyaz Ahmed which version of OpenLane & the PDK did you use?

@Amr Gouhar thankyou for your reply. The version of Openlane is RC5 and the PDK is Skywater 130 A. The library is "sky130_fd_sc_hd__tt_025C_1v80.lib".

@Ayyaz Ahmed: Are you seeing any improvements in the optimizations stage (post_openphsyn/post_optimizations)?