Hi @User , please feel free to commit directly to the PR. I think for threads it might make sense to use ARG so we can override based on available memory

Hi, Could anyone please tell why I am getting so much large delay for the highlighted cell in the below attached timing report? It is occurring in the reset path of flops. If it is due to high fanout then how I can handle this issue? I have synthesized the design in Openlane using yosys and performed STA using openSTA. Thanking you in anticipation.

@User @User Hello, I wanted to look at the information like minimum skew, maximum skew, insertion delay etc. at the CTS stage. I don't see this info in the log file and there are no files being generated under the

reports/cts

directory. Please guide me towards it. Thank you.

#231 Issue Regarding Placement error in OPENLANE RTL to GDS flow Issue opened by DarshanGuled Hello, This is Darshan here. We are working on OPENLANE FLOW. We have installed and tested example of SPM which was already present in the design folder. Now we are trying to add our own design like counter and D - FF design, but we are facing the following errors in the in Detailed Placement. Please Anyone help is to debug the error`` efabless/openlane

#232 Post-CTS Timing Reports Issue opened by agorararmard Is your feature request related to a problem? Please describe. No timing reports are generated in the CTS stage, although they are generated at various stages, and they're easy to add. Describe the solution you'd like In https://github.com/efabless/openlane/blob/master/scripts/openroad/or_cts.tcl report skew and timing information, after legalization. efabless/openlane

Is there an OpenRoad Channel here?

#232 Post-CTS Timing Reports Issue closed by ax3ghazy efabless/openlane

@User @User @User its coming togther… robtaylor/openlane@f84c4b0 (github.com)

#236 SYNTH_ADDER_TYPE=RCA also requires SYNTH_READ_BLACKBOX_LIB=1 Issue opened by antonblanchard Commit a421bf6 ("Add Ripple carry adder/Full adder mapping to yosys (#228)") adds

SYNTH_ADDER_TYPE

. I tried the

RCA

option but it fails with:

ERROR: Module `\sky130_fd_sc_hd__fa_1' referenced in module `\adder' in cell `$add$/openLANE_flow/designs/adder/src/adder.v:20$2.stage[0].FA' is not part of the design.

Adding access to the standard cells with

set ::env(SYNTH_READ_BLACKBOX_LIB) 1

fixes it. Since the design itself is not using standard cells this is a bit confusing. The

FA

doesn't have this issue, I'm guessing because we do that mapping later on. efabless/openlane

@User @User is anyone using hs cells? Wondering if I could implement a critical macro with hs cells, with the rest of the design using hd cells

@User could you take a look at the multiarch branch? I seem to be getting a ppc64le specific failure on klayout

#236 SYNTH_ADDER_TYPE=RCA also requires SYNTH_READ_BLACKBOX_LIB=1 Issue closed by ax3ghazy efabless/openlane

@User How is the openroad update going? Worth trying? I have a couple of things that fail with the older version of openroad but look to be fixed upstream

Is there a way of working back from the critical path in the timing report from OpenSTA to the names of the nets in the RTL?

Has anyone else seen the OpenLANE flow fail synthesis with Local parameters in module parameter port lists requires SystemVerilog.

image.png

yosys can read and synthesise designs like this

hmm, I was sure I had done this ok in the past. swapping localparam for parameter works

looks like parameter is the correct way to do this anyway

Is there any resources that can help to write TCL code to invoke OpenLANE in bash...

#249 sha3.v wrong implementation Issue opened by guidobertoni I was reading the code of sha3.v and noticed that the actual implementation in it is SHA2-512, you can read the end of file comment reporting sha512_core.v or read the implementation to see that is not containing the Keccak algorithm in it. line 595 contains the implementation of the Ch function of SHA 512 as described in https://en.wikipedia.org/wiki/SHA-2 this function is not part of the SHA3 algorithm efabless/openlane

#250 while doing synth_explore showing couldn't open the file! at /openLANE_flow/scripts/synth_exp/analyze.pl line 16. Issue opened by shafnaskm efabless/openlane

@User @User Guys, do I need anything else other than running the commands for installation of OpenLane ? Is there any procedure steps or just run the commands ?

@User @User I tested

remove_buffers

on a couple of designs. With the

aes

test case I still make timing and there's about 2000 less cells overall. It looks like yosys is pretty aggressive at adding buffers. Is it worth adding to the flow?

#250 while doing synth_explore showing couldn't open the file! at /openLANE_flow/scripts/synth_exp/analyze.pl line 16. Issue closed by agorararmard efabless/openlane

#231 Issue Regarding Placement error in OPENLANE RTL to GDS flow Issue closed by agorararmard efabless/openlane

#175 About constraints Issue closed by agorararmard efabless/openlane

where is pitch of metals is defined in openlane

can someone explain me what these numbers indicate for those metal layers