Matt Venn
02/19/2021, 3:33 PMJean
02/19/2021, 7:15 PMmodule #(
...
) frequency_counter (
...
);
Matt Venn
02/20/2021, 7:53 AMTom
02/20/2021, 8:16 PMlocalparam
instead of parameter
I think you'll nee to take the Verilog 2005 approach of having a coma separated port list and then declaring the ports under your localparam
deceleration in the module body. A bit of a nuisance I know.
module mymodule
(
bin_i,
onehot_o
);
parameter SZX;
localparam SZ=2**SZX;
input wire [SZX-1:0] bin_i;
output wire [SZ-1:0] onehot_o;
Jean
02/21/2021, 12:19 AMmodule mymodule #
(
parameter DATA_WIDTH = 32 // width of data bus in bits (8, 16, 32, or 64)
)
(
input [DATA_WIDTH-1:0] bin_i
)