@User @User I tested

remove_buffers

on a couple of designs. With the

aes

test case I still make timing and there's about 2000 less cells overall. It looks like yosys is pretty aggressive at adding buffers. Is it worth adding to the flow?

I can test it on all designs overnight today and we can see the effects on timing. You can also disable the yosys buffering with https://github.com/efabless/openlane/blob/db78d9ac670f59ab6cf01af1805fec9cacdbedee/configuration/synthesis.tcl#L20.

Thanks @Amr Gouhar

@Anton Blanchard: Sorry, I forgot to post the results online, here they are https://docs.google.com/spreadsheets/d/1TmdZAnJ65Y38fa49cKzBlA62-1ZbMyhnmKjKKqtbRfo/edit?usp=sharing Benchmark is without

remove_buffers

and User is with

remove_buffers

. There is a general increase in the wns; however, it's a slight increase -5ns max. On the other hand, the antenna violations and the wire length got reduced significantly for most designs as well as the runtime to route. I think this is something to consider adding to the flow at least if optionally. What's your opinion about that @Anton Blanchard & @Ahmed Ghazy? I haven't tried disabling

SYNTH_BUFFERING

from the start, still waiting on some computing resources to be available and then I'll give this one a shot.

Interesting results! It made me investigate why the resizer couldn't at least match yosys, and I ended up at: https://github.com/The-OpenROAD-Project/OpenROAD/pull/582

Cool!