Anton Blanchard
02/22/2021, 2:44 AMremove_buffers
on a couple of designs. With the aes
test case I still make timing and there's about 2000 less cells overall. It looks like yosys is pretty aggressive at adding buffers. Is it worth adding to the flow?Amr Gouhar
02/22/2021, 2:22 PMAnton Blanchard
02/22/2021, 6:53 PMAmr Gouhar
02/24/2021, 5:56 PMremove_buffers
and User is with remove_buffers
. There is a general increase in the wns; however, it's a slight increase -5ns max. On the other hand, the antenna violations and the wire length got reduced significantly for most designs as well as the runtime to route. I think this is something to consider adding to the flow at least if optionally. What's your opinion about that @Anton Blanchard & @Ahmed Ghazy?
I haven't tried disabling SYNTH_BUFFERING
from the start, still waiting on some computing resources to be available and then I'll give this one a shot.Anton Blanchard
02/25/2021, 8:11 AMAmr Gouhar
02/25/2021, 2:00 PM