# openlane

Olof Kindgren

04/12/2021, 6:59 AM
Trying to get a better picture of the timing for my macro. Seems like I'm passing timing at 100MHz but I wonder what
-2.00    8.00   output external delay
comes from. Feels like a placeholder value but perhaps I'm missing something

Matt Liberty

04/14/2021, 3:35 AM
I think it means it comes from an sdc constraint

Olof Kindgren

04/15/2021, 10:21 AM
Yes. Found it now. So with the simplified flow the user just supplies a clock period which is fed into a base sdc file template. This template also sets input/output delays as 0.2 * clk_period, which adds up to the number I see. I guess my question then would be why this value was chosen