In Caravel's openlane flow, it looks like timing is not being checked between blocks (unless I've missed something). To elaborate, in a commercial hierarchical flow, I would generate a Liberty file for my subblock from the post layout gate level netlist and spef file, and give this lib file to any blocks that instantiate my subblock. This way, I am able to check timing at the interface between blocks. Is this possible with openlane?

Not straightforward in OpenLANE, as currently there is no open-source library characterization engine. There is one project where we (VSD) are independently trying to create ILM kind of timing flow. That might help to some extent to analyse interface timing