Hi my design repo is <https://github.com/MSPDUTTA/...
# openlane
Hi my design repo is https://github.com/MSPDUTTA/Subservient_SOC and while doing make user_project_wrapper , my simulation is being terminated by the below error after every stage is being completed and error is coming for this file https://github.com/MSPDUTTA/Subservient_SOC/blob/main/verilog/rtl/user_project_wrapper.v .
When you implement the subservient and the sram as macros, you can't use the parameters in user_project_wrapper.v any more. I think you should remove the parameter and create the blackbox (you only need the inputs and outputs) for each macro with the parameters replaced by the actual values.
Thanks a lot! It got resolved after removing parameters with direct values required