Hi , my design repo is https://github.com/MSPDUTTA/Subservient_SOC and while doing make user_project_wrapper , the simulation is waiting for a very long time at current_step_index . Should I continue to wait or should check for any error by killing the simulation? Is it expected to take such a long time?

Extraction can be quite slow. How long has it taken?

It took more than 4 hours in our server then failed with this error:

Extracting user_project_wrapper into user_project_wrapper.ext:
Created database crash recovery file /tmp//MAG4295.6o2gMr
user_project_wrapper: 1398 fatal errors
Total of 1398 errors (check feedback entries).
exttospice finished.
Using technology "sky130A", version 1.0.156-0-g7e29496
[ERROR]: There are illegal overlaps (e.g., routes over obstructions) in your design.
[ERROR]: See /project/openlane/user_project_wrapper/runs/user_project_wrapper/logs/magic/42-magic_ext2spice.feedback.txt for more.
[INFO]: Calculating Runtime From the Start...
[INFO]: Flow failed for user_project_wrapper/29-05_22-47 in 4h18m38s
[INFO]: Generating Final Summary Report...
[INFO]: Design Name: user_project_wrapper
Run Directory: /project/openlane/user_project_wrapper/runs/user_project_wrapper
Source not found.
----------------------------------------

Any suggestions how to resolve ? There is no magic drc error in the design if I open the routing/user_project_wrapper.def using magic and check for drc error and there was no routing violations so routing stage went through.

You might need to block routing over the macro. That means you need to create a placement/routing blockage in the region of macro from metal4 downward.

Aren't macros already blocked from m4 down?

Furthermore, I try to implement your project as macros only. But I found out that you have some logics (add & shift) in your top-level design (user_project_wrapper.v). Maybe, you can put these logics inside your subservient macro. Then, the top-level user_project_wrapper only wires these macros.

Thanks for the suggestions. I updated the subservient module to include extra logic and kept just two macros in top and updated wrapper/config.tcl accordingly , so now those steps got through and my flow completed.

I believe it is something related to the SRAM. You can open the design in magic to see what is actually happening. Would you please update your code in github? I will try to take a look.

yes my code is updated to github

The SRAM will have DRC errors since it uses "core memory" design rules. These aren't checked by magic properly. OpenLane needs to work out how the precheck can use the LEF for the memory cells instead of the GDS.