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#openlane
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# openlane
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Tayyeb Mahmood

06/04/2021, 9:51 AM
@User Hi, Should I assume there is no support of register retiming in Yosys?
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Matt Venn

06/04/2021, 10:05 AM
I don't know what that means, can you explain?
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Tayyeb Mahmood

06/04/2021, 10:10 AM
Register retiming is a common technique in commercial synthesis tools. In a nutshell, it is ability of tool to move FFs (in a pipelined design) forward or backward in order to balance the stage delays.
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Hieu Bui

06/04/2021, 10:11 AM
You can use the synthesis exploration mode in Openlane to choose the best synthesis strategy for your design. Openlane predefines 6 strategies. Some are for timing optimization, some are for area optimization. For reg retiming, I have no idea.
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Matthew Guthaus

06/04/2021, 11:54 AM
But it doesn't do register retiming AFAIK
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Kevin Dai

06/04/2021, 7:21 PM
Afaik I recall abc having a retime and relut option here: http://www.clifford.at/yosys/cmd_synth_ice40.html Not sure if applicable but hopefully this helps.
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Tayyeb Mahmood

06/05/2021, 5:35 AM
A small dive into ABC codebase asserted that it does support retiming. But openlane's flow does not, I will however experiment and report. Thanks @Kevin Dai
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Kevin Dai

06/05/2021, 5:56 AM
Though you can (I think) run the flow with -dff passed to abc additionally. I've never tried and can't comment on if it'll work.
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Russell Friesenhahn

06/05/2021, 8:48 PM
nice, this would be cool. Enables my lazier coding
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Tayyeb Mahmood

06/08/2021, 6:34 PM
retime is used in provided flow, but somehow it is not pushing any register a bit. I will do rigorous testing after 18th.
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Russell Friesenhahn

06/08/2021, 7:34 PM
maybe the specified clock rates are not pushing the tools to do it
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Tayyeb Mahmood

06/09/2021, 7:28 AM
I actually changed the clock rate to make it push. From the source code of ABC, it us able to move registers forward and backward, but how, I still do not know. However, I have dumped blif for later experiments.