@User Hi, Should I assume there is no support of register retiming in Yosys?

I don't know what that means, can you explain?

Register retiming is a common technique in commercial synthesis tools. In a nutshell, it is ability of tool to move FFs (in a pipelined design) forward or backward in order to balance the stage delays.

You can use the synthesis exploration mode in Openlane to choose the best synthesis strategy for your design. Openlane predefines 6 strategies. Some are for timing optimization, some are for area optimization. For reg retiming, I have no idea.

But it doesn't do register retiming AFAIK

Afaik I recall abc having a retime and relut option here: http://www.clifford.at/yosys/cmd_synth_ice40.html Not sure if applicable but hopefully this helps.

A small dive into ABC codebase asserted that it does support retiming. But openlane's flow does not, I will however experiment and report. Thanks @Kevin Dai

Hmm that's interesting. Though what does this do? https://github.com/The-OpenROAD-Project/OpenLane/blob/f7412929e8775504b9bdc5f247b7f967849a1fc3/scripts/synth.tcl#L113

nice, this would be cool. Enables my lazier coding

retime is used in provided flow, but somehow it is not pushing any register a bit. I will do rigorous testing after 18th.

maybe the specified clock rates are not pushing the tools to do it

I actually changed the clock rate to make it push. From the source code of ABC, it us able to move registers forward and backward, but how, I still do not know. However, I have dumped blif for later experiments.