# openlane

Matt Venn

06/09/2021, 11:23 AM
Warning! The default behaviour for OpenLANE is now to add clock buffers on all output pins (I assume to improve drive strength from the macro). Which is probably fine for your design, but if like me you are relying on tristate buffers being the last thing, this won't happen without explicitly turning off this setting: PL_RESIZER_BUFFER_OUTPUT_PORTS
👍 2
Thank goodness for GL simulation and many eyes 😅