@Manar Abdelatty Any idea about this? It is generating many GB of logs too: -rw-r--r-- 1 mrg mrg 1329836564 Jun 14 11:36 openlane/openram_testchip/runs/openram_testchip/logs/floorplan/7-pdn.log

This is what the start of the pdn log looks like:

OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /software/PDKs/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib line 31, default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/openram_testchip/runs/openram_testchip/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 440 library cells
Notice 0: Finished LEF file:  /project/openlane/openram_testchip/runs/openram_testchip/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/openram_testchip/runs/openram_testchip/results/floorplan/openram_testchip.floorplan.def
Notice 0: Design: openram_testchip
Notice 0:     Created 1407 pins.
Notice 0:     Created 34934 components and 79791 component-terminals.
Notice 0:     Created 2129 nets and 3535 connections.
Notice 0: Finished DEF file: /project/openlane/openram_testchip/runs/openram_testchip/results/floorplan/openram_testchip.floorplan.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016]   config: /software/PDKs/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is openram_testchip
[INFO] [PDNG-0009] Reading technology data
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
    Stdcell Rails
      Layer: met1 -  width: 0.480  pitch: 2.720  offset: 0.000 
    Straps
      Layer: met4 -  width: 1.600  pitch: 153.600  offset: 16.320 
    Connect:  {met1 met4}
Type: macro, macro_1
    Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
    Straps
    Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0015] Writing to database
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vccd1 is not explicitly set.
[WARNING PSM-0022] Using voltage 0.000V for VDD network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vccd1.
[WARNING PSM-0030] Vsrc location at (5.520um, 10.880um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (21.840um, 10.800um).
[WARNING PSM-0030] Vsrc location at (145.520um, 10.880um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (175.440um, 10.800um)
.

It seems that disabling the supply connectivity check solves this: set ::env(FP_PDN_CHECK_NODES) 0

It made a 4GB log and ran all night