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#openlane
Title
# openlane
z

Zachary Ellis

06/15/2021, 1:30 AM
Is there any reason why a macro would be placed twice when running the "user_project_wrapper" through openlane. The wrapper always fails at step 35 because of overlaping components and looking at the xor screenshot from klayout it looks like it is trying to place the same macro twice. Here is the screenshot
this is my config file if that helps
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#      <http://www.apache.org/licenses/LICENSE-2.0>
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0

# Base Configurations. Don't Touch
# section begin
set script_dir [file dirname [file normalize [info script]]]

source $script_dir/../../caravel/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl

set ::env(DESIGN_NAME) user_project_wrapper
#section end

# User Configurations

## Source Verilog Files
set ::env(VERILOG_FILES) "\
    $script_dir/../../caravel/verilog/rtl/defines.v \
    $script_dir/../../verilog/rtl/user_project_wrapper.v"

## Clock configurations
set ::env(CLOCK_PORT) "user_clock2"
set ::env(CLOCK_NET) "mprj.clk"

set ::env(CLOCK_PERIOD) "10"

## Internal Macros
### Macro Placement
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg

### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
    $script_dir/../../caravel/verilog/rtl/defines.v \
    $script_dir/../../verilog/rtl/user_proj_example.v"

set ::env(EXTRA_LEFS) "\
    $script_dir/../../lef/user_proj_example.lef"

set ::env(EXTRA_GDS_FILES) "\
    $script_dir/../../gds/user_proj_example.gds"

set ::env(GLB_RT_MAXLAYER) 5

set ::env(FP_PDN_CHECK_NODES) 0

# The following is because there are no std cells in the example wrapper project.
set ::env(SYNTH_TOP_LEVEL) 1
set ::env(PL_RANDOM_GLB_PLACEMENT) 1

set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0

set ::env(DIODE_INSERTION_STRATEGY) 0
set ::env(FILL_INSERTION) 0
set ::env(TAP_DECAP_INSERTION) 0
set ::env(CLOCK_TREE_SYNTH) 0
b

Baloch

06/15/2021, 8:00 AM
Facing same issue
k

Konrad Wilk

06/15/2021, 12:29 PM
Does the macro.cfg have one entry?
b

Baloch

06/15/2021, 12:44 PM
Yes, for me it only has one entry
z

Zachary Ellis

06/15/2021, 1:51 PM
Yes only one
m

Matthew Ballance

06/15/2021, 9:28 PM
From the screenshot name, it seems you're looking at the 'xor' GDS file. Might be worth checking the other (non-xor) one. I have seen some oddities in the 'xor' GDS file, while the non-xor looked perfectly fine. I know this isn't an explanation, but worth checking 😉
z

Zachary Ellis

06/15/2021, 9:47 PM
Yes the non xor one looks fine. I’m not really sure what’s causing the overlap errors though. Or how to get rid of them
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