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I still haven't been able to resolve an issue with...
# openlane
m
I still haven't been able to resolve an issue with clock nets out of logic. I made a clock mux in my design as a separate module so that I can properly refer to a port in CLOCK_PORT as well as CLOCK_NET. I have this:
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clock_mux clkmux(.clk0(faast_clk),                                                                                                         
                     .clk1(slow_clk),                                                                                   
                    .sel(in_select),                                                                                   
                    .clk(clk));
and I define
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set ::env(CLOCK_PORT) "clkmux.clk"                                                                                     
set ::env(CLOCK_NET) "clk"
but then I get this error during CTS because Yosys tries to buffer the clock and the clock net name changes:
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[WARNING STA-0337] port 'clkmux.clk' not found.
[INFO]: Setting output delay to: 2.0
[INFO]: Setting input delay to: 2.0
[WARNING STA-0337] port 'clkmux.clk' not found.
[INFO]: Setting load to: 0.01765
[INFO]: Configuring cts characterization...
[INFO]: Performing clock tree synthesis...
[INFO]: Looking for the following net(s): clk
[INFO]: Running Clock Tree Synthesis...
[ERROR UKN-0000] Error when finding -clk_nets in DB!
Error: or_cts.tcl, 57 UKN-0000
If I do set ::env(CLOCK_NET) "clkmux.clk" instead, it says that it only has one sink (the output of the clkmux module). What can I do?
m
@Matthew Guthaus Does 
clkmux.clk
really have one sink ? you can check the synthesized netlist to see what is the name of the net connected to the 
CLK
pin of the flip flops
m
Inside of the module clkmux, it does, yes. Outside of that, it also has one because it is the root of a buffer tree that Yosys made
- clkmux.clk ( repeater1500 A ) ( 4410 X ) + USE SIGNAL ; 4410 is the output of a mux and repeater1500 is the root of a buffer tree
Here is the fanout of that repeater: - net1498 ( 4655 CLK ) ( 4657 CLK ) ( 4659 CLK ) ( 4739 CLK ) ( 4726 CLK ) ( 4730 CLK ) ( 4731 CLK ) ( 4729 CLK ) ( 4727 CLK ) ( 4728 CLK ) ( 4679 CLK ) ( 4678 CLK ) ( 4667 CLK ) ( 4668 CLK ) ( _4669\ _ CLK ) ( 4665 CLK ) ( 4656 CLK ) ( 4666 CLK ) ( 4658 CLK ) ( 4654 CLK ) ( 4652 CLK ) ( 4653 CLK ) ( _4677\ _ CLK ) ( 4681 CLK ) ( 4680 CLK ) ( 4716 CLK ) ( 4719 CLK ) ( 4715 CLK ) ( 4674 CLK ) ( 4721 CLK ) ( _4672\ _ CLK ) ( 4673 CLK ) ( 4664 CLK ) ( 4663 CLK ) ( 4662 CLK ) ( 4718 CLK ) ( 4717 CLK ) ( 4720 CLK ) ( _4661\ _ CLK ) ( 4660 CLK ) ( 4670 CLK ) ( 4671 CLK ) ( 4676 CLK ) ( 4675 CLK ) ( repeater1498 X ) + USE SIGNAL ; - net1499 ( 4759 CLK ) ( 4760 CLK ) ( 4761 CLK ) ( 4757 CLK ) ( 4758 CLK ) ( 4746 CLK ) ( 4702 CLK ) ( 4714 CLK ) ( 4755 CLK ) ( 4752 CLK ) ( 4754 CLK ) ( 4756 CLK ) ( 4762 CLK ) ( 4753 CLK ) ( _4749\ _ CLK ) ( 4751 CLK ) ( 4748 CLK ) ( 4750 CLK ) ( 4747 CLK ) ( 4689 CLK ) ( 4688 CLK ) ( 4690 CLK ) ( _4691\ _ CLK ) ( 4703 CLK ) ( 4704 CLK ) ( 4712 CLK ) ( 4713 CLK ) ( 4742 CLK ) ( 4743 CLK ) ( 4744 CLK ) ( _4745\ _ CLK ) ( 4693 CLK ) ( 4694 CLK ) ( 4687 CLK ) ( repeater1499 X ) + USE SIGNAL ; - net1500 ( 4699 CLK ) ( 4697 CLK ) ( 4698 CLK ) ( 4724 CLK ) ( 4725 CLK ) ( 4723 CLK ) ( 4732 CLK ) ( 4741 CLK ) ( 4737 CLK ) ( 4740 CLK ) ( 4738 CLK ) ( 4736 CLK ) ( 4733 CLK ) ( 4734 CLK ) ( repea\ ter1498 A ) ( 4722 CLK ) ( 4735 CLK ) ( 4682 CLK ) ( 4684 CLK ) ( 4683 CLK ) ( 4651 CLK ) ( repeater1499 A ) ( _\ 4685_ CLK ) ( 4686 CLK ) ( 4696 CLK ) ( 4695 CLK ) ( 4705 CLK ) ( 4706 CLK ) ( 4711 CLK ) ( 4710 CLK ) ( _4707\ _ CLK ) ( 4692 CLK ) ( 4701 CLK ) ( 4700 CLK ) ( 4708 CLK ) ( 4709 CLK ) ( repeater1500 X ) + USE SIGNAL ;
m
@Matthew Guthaus But, what is the name of the net connected to the CLK pin of the flip flops in the synthesized netlist ?
m
net1498, net1499, net1500
(it is shown above)
In the behavioral netlist, it is clk, the output of clkmux
So Yosys made a buffer tree repeater1500 -> (repeater1499, repeater1498)
In the synthesized_optimized.v:
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sky130_fd_sc_hd__buf_12 repeater1498 (.A(net1500),                                                                    
    .X(net1498));                                                                                                      
 sky130_fd_sc_hd__buf_8 repeater1499 (.A(net1500),                                                                     
    .X(net1499));                                                                                                      
 sky130_fd_sc_hd__buf_12 repeater1500 (.A(\clkmux.clk ),                                                               
    .X(net1500));  
 sky130_fd_sc_hd__dfxtp_4 _4651_ (.D(_0333_),                                                                          
    .Q(net1225),                                                                                                       
    .CLK(net1500));                                                                                                    
 sky130_fd_sc_hd__dfxtp_4 _4652_ (.D(_0334_),                                                                          
    .Q(net1236),                                                                                                       
    .CLK(net1498));                                                                                                    
 sky130_fd_sc_hd__dfxtp_4 _4653_ (.D(_0335_),                                                                          
    .Q(net1247),                                                                                                       
    .CLK(net1498));
etc
m
@Matthew Guthaus You will need to set 
CLOCK_NET
as a list of 
net1498, net1499, net1500
, This way tritoncts will buffer each net
@Matthew Guthaus I think another solution would be to disable 
SYNTH_BUFFERING
if you want to eliminate the buffer tree and let resizer handle the timing optimizations
m
That will buffer each of those as a separate tree
That second option might work...
Even disabling SYNTH_BUFFERING results in a buffered fanout from the clkmux
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sky130_fd_sc_hd__buf_12 repeater1581 (.A(\clkmux.clk ),                                                               
    .X(net1581));    
 sky130_fd_sc_hd__buf_12 repeater1579 (.A(net1580),                                                                    
    .X(net1579));                                                                                                      
 sky130_fd_sc_hd__buf_12 repeater1580 (.A(net1581),                                                                    
    .X(net1580)); 
 sky130_fd_sc_hd__dfxtp_4 _3965_ (.D(_0335_),                                                                          
    .Q(net1247),                                                                                                       
    .CLK(net1580));                                                                                                    
 sky130_fd_sc_hd__dfxtp_4 _3966_ (.D(_0336_),                                                                          
    .Q(net1258),                                                                                                       
    .CLK(net1581));                                                                                                    
 sky130_fd_sc_hd__dfxtp_1 _3967_ (.D(_0337_),                                                                          
    .Q(net1158),                                                                                                       
    .CLK(net1580));
with it disabled ^^
m
@Matthew Guthaus Looks like 
SYNTH_BUFFERING
is only for abc, not sure what is the impact of that but you can try commenting the insbuf command here https://github.com/The-OpenROAD-Project/OpenLane/blob/f7412929e8775504b9bdc5f247b7f967849a1fc3/scripts/synth.tcl#L341
m
That didn't seem to do anything
@Manar Abdelatty It seems that this buffering is done in step 8-resizer
m
@Matthew Guthaus This is the resizer design optimization step, you can skip it by setting 
PL_RESIZER_DESIGN_OPTIMIZATIONS
to zero
m
I did that and now it segfaults: [ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/openroad/or_resizer_timing.tcl |& tee >&@stdout /project/openlane/user_project_wrapper/runs/user_project_wrapper/logs/placement/18-resizer_timing.log" [ERROR]: Exit code: 1 [ERROR]: Last 10 lines: child killed: segmentation violation
If I also disable PL_RESIZER_TIMING_OPTIMIZATIONS it doesn't
The timing is horrible now, but at least it works?
so far
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