Matthew Guthaus
06/17/2021, 1:05 PMclock_mux clkmux(.clk0(faast_clk),
.clk1(slow_clk),
.sel(in_select),
.clk(clk));
and I define
set ::env(CLOCK_PORT) "clkmux.clk"
set ::env(CLOCK_NET) "clk"
but then I get this error during CTS because Yosys tries to buffer the clock and the clock net name changes:
[WARNING STA-0337] port 'clkmux.clk' not found.
[INFO]: Setting output delay to: 2.0
[INFO]: Setting input delay to: 2.0
[WARNING STA-0337] port 'clkmux.clk' not found.
[INFO]: Setting load to: 0.01765
[INFO]: Configuring cts characterization...
[INFO]: Performing clock tree synthesis...
[INFO]: Looking for the following net(s): clk
[INFO]: Running Clock Tree Synthesis...
[ERROR UKN-0000] Error when finding -clk_nets in DB!
Error: or_cts.tcl, 57 UKN-0000
If I do set ::env(CLOCK_NET) "clkmux.clk" instead, it says that it only has one sink (the output of the clkmux module). What can I do?Manar Abdelatty
06/17/2021, 1:20 PMclkmux.clk
really have one sink ? you can check the synthesized netlist to see what is the name of the net connected to the CLK
pin of the flip flopsMatthew Guthaus
06/17/2021, 1:21 PMManar Abdelatty
06/17/2021, 1:27 PMMatthew Guthaus
06/17/2021, 1:28 PMsky130_fd_sc_hd__buf_12 repeater1498 (.A(net1500),
.X(net1498));
sky130_fd_sc_hd__buf_8 repeater1499 (.A(net1500),
.X(net1499));
sky130_fd_sc_hd__buf_12 repeater1500 (.A(\clkmux.clk ),
.X(net1500));
sky130_fd_sc_hd__dfxtp_4 _4651_ (.D(_0333_),
.Q(net1225),
.CLK(net1500));
sky130_fd_sc_hd__dfxtp_4 _4652_ (.D(_0334_),
.Q(net1236),
.CLK(net1498));
sky130_fd_sc_hd__dfxtp_4 _4653_ (.D(_0335_),
.Q(net1247),
.CLK(net1498));
etcManar Abdelatty
06/17/2021, 1:32 PMCLOCK_NET
as a list of net1498, net1499, net1500
, This way tritoncts will buffer each netSYNTH_BUFFERING
if you want to eliminate the buffer tree and let resizer handle the timing optimizationsMatthew Guthaus
06/17/2021, 1:37 PMsky130_fd_sc_hd__buf_12 repeater1581 (.A(\clkmux.clk ),
.X(net1581));
sky130_fd_sc_hd__buf_12 repeater1579 (.A(net1580),
.X(net1579));
sky130_fd_sc_hd__buf_12 repeater1580 (.A(net1581),
.X(net1580));
sky130_fd_sc_hd__dfxtp_4 _3965_ (.D(_0335_),
.Q(net1247),
.CLK(net1580));
sky130_fd_sc_hd__dfxtp_4 _3966_ (.D(_0336_),
.Q(net1258),
.CLK(net1581));
sky130_fd_sc_hd__dfxtp_1 _3967_ (.D(_0337_),
.Q(net1158),
.CLK(net1580));
with it disabled ^^Manar Abdelatty
06/17/2021, 1:49 PMSYNTH_BUFFERING
is only for abc, not sure what is the impact of that but you can try commenting the insbuf command here https://github.com/The-OpenROAD-Project/OpenLane/blob/f7412929e8775504b9bdc5f247b7f967849a1fc3/scripts/synth.tcl#L341Matthew Guthaus
06/17/2021, 3:07 PMManar Abdelatty
06/17/2021, 5:26 PMPL_RESIZER_DESIGN_OPTIMIZATIONS
to zeroMatthew Guthaus
06/17/2021, 6:03 PM